M. Schmidt

Intrinsic and extrinsic corrugation of monolayer graphene deposited on SiO 2

Using scanning tunneling microscopy in an ultrahigh vacuum and atomic force microscopy, we investigate the corrugation of graphene flakes deposited by exfoliation on a Si/SiO2 (300 nm) surface. While the corrugation on SiO2 is long range with a correlation length of about 25 nm, some of the graphene monolayers exhibit an additional corrugation with a preferential wavelength of about 15 nm. A detailed analysis shows that the long-range corrugation of the substrate is also visible on graphene, but with a reduced amplitude, leading to the conclusion that the graphene is partly freely suspended between hills of the substrate. Thus, the intrinsic rippling observed previously on artificially suspended graphene can exist as well, if graphene is deposited on SiO2.

Interface Defects in HfO2, LaSiOx, and Gd2O3 High-k/Metal-Gate Structures on Silicon

In this work, we present experimental results examining the energy distribution of the relatively high (> 1 X 10(11) cm(-2)) electrically active interface defects which are commonly observed in high-dielectric-constant (high-k) metal-insulator-silicon systems during high-k process development. This paper extends previous studies on the Si(100)/SiOx/HfO2 system to include a comparative analysis of the density and energy distribution of interface defects for HfO2, lanthanum silicate (LaSiOx), and Gd2O3 thin films on (100) orientation silicon formed by a range of deposition techniques. The analysis of the interface defect density across the energy gap, for samples which experience no H-2/N-2 annealing following the gate stack formation, reveals a peak density (similar to 2 X 10(12) cm(-2) eV(-1) to similar to 1 X 10(13) cm(-2) eV(-1)) at 0.83-0.92 eV above the silicon valence bandedge for the HfO2, LaSiOx, and Gd2O3 thin films on Si (100). The characteristic peak in the interface state density (0.83-0.92 eV) is obtained for samples where no interface silicon oxide layer is observed from transmission electron microscopy. Analysis suggests silicon dangling bond (P-bo) centers as the common origin for the dominant interface defects for the various Si(100)/SiOx/high-k/metal gate systems. The results of forming gas (H-2/N-2) annealing over the temperature range 350-555 degrees C are presented and indicate interface state density reduction, as expected for silicon dangling bond centers. The technological relevance of the results is discussed. (c) 2007 The Electrochemical Society.

0.86-nm CET Gate Stacks With Epitaxial

In this letter, ultrathin gadolinium oxide (Gd2O3 ) high-k gate dielectrics with complementary-metal-oxide-semiconductor (CMOS)-compatible fully silicided nickel-silicide metal gate electrodes are reported for the first time. MOS capacitors with a Gd2O3 thickness of 3.1 nm yield a capacitance equivalent oxide thickness of CET=0.86 nm. The extracted dielectric constant is k=13-14. Leakage currents and equivalent oxide thicknesses of this novel gate stack meet the International Technology Roadmap for Semiconductors targets for the near term schedule and beyond

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We investigate the impact of rapid thermal anneals on structural and electrical properties of crystalline Gd2O3 layers grown on Si with different orientations. Due to additional oxygen from the annealing ambient, a structureless two-layer stack (silicon-oxide-like and silicate-like) between the silicon and the crystalline oxide will be formed. The degradation of layers can be significantly reduced by sealing the layer with a-Si prior to annealing. For the capped layers, the effective capacitance equivalent thickness increases only slightly even after a 1000 °C anneal.

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The authors report on the investigation of amorphous Gd-based silicates as high- k dielectrics. Two different stacks of amorphous gadolinium oxide (Gd2 O3) and silicon oxide (Si O2) on silicon substrates are compared after annealing at temperatures up to 1000 °C. Subsequently formed metal oxide semiconductor capacitors show a significant reduction in the capacitance equivalent thicknesses after annealing. Transmission electron microscopy, medium energy ion scattering, and x-ray diffraction analysis reveal distinct structural changes such as consumption of the Si O2 layer and formation of amorphous Gd silicate. The controlled formation of Gd silicates in this work indicates a route toward high- k dielectrics compatible with conventional, gate first complementary metal-oxide semiconductor integration schemes.

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It is argued that the subtle crossover from decoherence-dominated classical magnetism to fluctuation-dominated quantum magnetism is experimentally accessible in graphene nanoribbons. We show that the width of a nanoribbon determines whether the edge magnetism is on the classical side, on the quantum side, or in between. In the classical regime, decoherence is dominant and leads to static spin polarizations at the ribbon edges, which are well described by mean-field theories. The quantum Zeno effect is identified as the basic mechanism which is responsible for the spin polarization and thereby enables the application of graphene in spintronics. On the quantum side, however, the spin polarization is destroyed by dynamical processes. The great tunability of graphene magnetism thus offers a viable route for the study of the quantum-classical crossover.

Dielectrics and FUSI NiSi Metal Electrodes

In this paper, epitaxial gadolinium oxide (Gd2O3) is reviewed as a potential high-K gate dielectric, both “as deposited” by molecular beam epitaxy as well as after integration into complementary metal oxide semiconductor (CMOS) processes. The material shows promising intrinsic properties, meeting critical ITRS targets for leakage current densities even at subnanometer equivalent oxide thicknesses. These epitaxial oxides can be integrated into a CMOS platform by a “gentle” replacement gate process. While high temperature processing potentially degrades the material, a route toward thermally stable epitaxial Gd2O3 gate dielectrics is explored by carefully controlling the annealing conditions.

Stability of crystalline Gd2O3 thin films on silicon during rapid thermal annealing

A triple step alignment process for UV nanoimprint lithography (UV-NIL) for the fabrication of nanoscale fin field effect transistors (FinFETs) is presented. An alignment accuracy is demonstrated between two functional layers of less than 20nm (3σ). The electrical characterization of the FinFETs fabricated by a full NIL process demonstrates the potential of UV-NIL for future nanoelectronic devices.

Gd silicate: A High-k Dielectric Compatible with High Temperature Annealing

We report on leakage current mechanisms in epitaxial gadolinium oxide (Gd(2)O(3)) high-k gate dielectrics suitable for low standby power logic applications. The investigated p-type metal-oxide-semi con doctor capacitors are gated with complementary-metal-oxide-semiconductor-compatible fully silicided nickel silicide electrodes. The Gd(2)O(3) thickness is 5.9 nm corresponding to a capacitance equivalent oxide thickness of 1.8 nm. Poole-Frenkel conduction is identified as the main leakage mechanism with the high-frequency permittivity describing the dielectric response on the carriers. A trap level of Phi(T) = 1.2 eV is extracted. The resulting band diagram strongly suggests hole conduction to be dominant over electron conduction.

Quantum Nature of Edge Magnetism in Graphene

Two process concepts for integration of novel gate stacks with epitaxial high-k dielectrics and metal gate electrodes are presented. A gate first process based on a planar gate stack on ultra thin SOI material has been used for successful fabrication of MOSFETs with TiN/Gd 2O3 gate stack. Furthermore MOSFETs with W/Gd2O3 gate stack have been fabricated with a replacement gate process. This is the first successful attempt to integrate crystalline high-K dielectrics into a gentle damascene metal gate process in order to reduce process induced oxide damages