A. Schäfer

Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors

Inverters based on uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field-effect transistors (TFETs) are fabricated. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n TFETs. The steep junctions formed by dopant segregation at low temperatures improve the band-to-band tunneling, resulting in higher on-currents of n- and p-TFETs of > 10 μA/μm at VDS=0.5 V. The subthreshold slope for n-channel TFETs reaches a minimum value of 30 mV/dec, and is <; 60 mV/dec over one order of magnitude of drain current. The first sSi NW complementary TFET inverters show sharp transitions and fairly high static gain even at very lowVDD=0.2 V. The first transient response analysis of the inverters shows clear output voltage overshoots and a fall time of 2 ns at VDD=1.0 V.

Demonstration of improved transient response of inverters with steep slope strained Si NW TFETs by reduction of TAT with pulsed I-V and NW scaling

We present gate all around strained Si (sSi) nanowire array TFETs with high I_ON (64μA/μm at V_DD=1.0V). Pulsed I-V measurements provide small SS and record I₆₀ of 1×10^-2μA/μm at 300K due to the suppression of trap assisted tunneling (TAT). Scaling the nanowires to 10 nm diameter greatly suppresses the impact of TAT and improves SS and I_ON. Transient analysis of complementary TFET inverters demonstrates experimentally for the first time that device scaling and improved electrostatics yields to faster time response.

Line and Point Tunneling in Scaled Si/SiGe Heterostructure TFETs

In this letter, we systematically investigate the impact of gate length and channel orientation on the electrical performance of tunneling field-effect transistors (TFETs). We fabricate and characterize Si/SiGe heterostructure TFETs with p-doped compressively strained Si0.5Ge0.5 source, intrinsic Si channel, and n-doped Si drain. We observe a linear relation of gate length, Lg, and ON-current, ION, which is the first experimental proof of line tunneling occurring in a TFET. TCAD simulations support our observations. After forming gas annealing, short-channel TFETs exhibit different I-V characteristics compared with long-channel devices due to better passivation.

Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications

Guided by the Wentzel-Kramers-Brillouin approximation for band-to-band tunneling (BTBT), various performance boosters for Si TFETs are presented and experimentally verified. Along this line, improvements achieved by the implementation of uniaxial strain in nanowires (NW), the benefits of high-k/metal gates, and newly engineered tunneling junctions as well as the effect of scaling the NW to diameters of 10 nm are demonstrated. Specifically, self-aligned ion implantation into the source/drain silicide and dopant segregation has been exploited to achieve steep tunneling junctions with less defects. The obtained devices deliver high on-currents, e.g., gate-all-around (GAA) NW p-TFETs with 10 nm diameter show ID = 64 μA/μm at VDS = VGS - Voff = -1.0 V, and good inverse subthreshold slopes (SS). Tri-gate TFETs reach minimum SS of 30 mV/dec. Dopant segregation helps to minimize the defect density in the junction and thus trap assisted tunneling (TAT) is reduced. Pulsed current-voltage (I-V) measurements have been used to investigate TAT. We could show that scaled NW devices with multigates are less vulnerable to TAT compared to planar devices due to a shorter tunneling path enabled by the inherently good electrostatics. Furthermore, SiGe NW homo- and heterojunction TFETs have been investigated. The advantages of a SiGe/Si heterostructure as compared to a homojunction device are revealed and the effect of line tunneling which results in an increased BTBT generation is demonstrated. It is also shown that complementary strained Si TFET inverters and p-TFET NAND gates can be operated at VDD as low as 0.2 V. This suggests a great potential of TFETs for ultralow power applications. The analysis of GAA NW TFETs for analog applications provided a high transconductance efficiency and large intrinsic gain, even higher than for state-of-the-art 20 nm FinFETs at low voltages.

Unipolar behavior of asymmetrically doped strained Si0.5Ge0.5 tunneling field-effect transistors

We investigate here the impact of the dopant concentration in the source and drain regions on the ambipolar behavior of band-to-band tunneling field-effect transistors with compressively strained Si0.5Ge0.5 channels grown on Si on insulator. Source and drain areas were formed by BF2+ and As+ ion implantation to doses of 1 × 1013, 1 × 1014, and 1 × 1015 cm−2. We show that the dopant concentration impacts the energy band alignment of source/drain and the channel region, and thus influences the tunneling current. The ambipolar device behavior is strongly reduced toward unipolar for source-to-drain implantation dose ratio of 100, but at the expense of the on-current, as compared to symmetric implanted devices. Moreover, our results indicate that for SiGe devices, the change of the B doping concentration has a greater impact on the tunneling currents than the variation of the As concentration.

Tuning thermal conductivity in homoepitaxial SrTiO3 films via defects

We demonstrate the ability to tune the thermal conductivity of homoepitaxial SrTiO3 films deposited by reactive molecular-beam epitaxy by varying growth temperature, oxidation environment, and cation stoichiometry. Both point defects and planar defects decrease the longitudinal thermal conductivity (k33), with the greatest decrease in films of the same composition observed for films containing planar defects oriented perpendicular to the direction of heat flow. The longitudinal thermal conductivity can be modified by as much as 80%—from 11.5 W m−1K−1 for stoichiometric homoepitaxial SrTiO3 to 2 W m−1K−1 for strontium-rich homoepitaxial Sr1+δTiOx films—by incorporating (SrO)2 Ruddlesden-Popper planar defects.

Low frequency noise in strained silicon nanowire array MOSFETs and Tunnel-FETs

MOSFETs and Tunnel-FETs (TFETs) based on arrays of nanowires (NWs) with 10 × 10 nm2 cross-section have been fabricated with strained silicon on insulator substrates. MOSFET devices show near ideal subthreshold slope close to 60 mV/dec proving excellent channel control achieved by high-k/metal gate stack. As expected fundamental differences between MOSFETs and TFETs in current-voltage characteristics are observed and analyzed. Low frequency noise spectra are studied for both types of devices. The devices show different behavior in terms of noise spectral density as a function of the applied gate voltage. A Hooge parameter of α = 7.3 × 10-3 is derived for the NW MOSFETs.

SiGe on SOI nanowire array TFETs with homo- and heterostructure tunnel junctions

This paper presents experimental results on tunneling field-effect transistors (TFETs) based on SiGe on SOI nanowire arrays. A SiGe-Si heterostructure TFET with a vertical tunneling junction consisting of an in situ doped SiGe source and a Si channel is demonstrated. The device shows switching behavior over a drain current range of up to 8 orders of magnitude with a minimum slope of 90 mV/dec. A larger tunneling area results in an increase of on-current. The heterojunction TFET shows great improvement compared to a homojunction SiGe on SOI nanowire design with implanted junctions. Temperature dependent measurements and device simulations are performed in order to analyze the tunnel transport mechanism in the devices.

Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped Nisi 2 tunnel junctions

Planar and nanowire (NW) tunneling field effect transistors (TFETs) have been fabricated on ultra thin strained and unstrained SOI with shallow doped Nickel disilicide (NiSi2) source and drain (S/D) contacts. We developed a novel, self-aligned process to form the p-i-n TFETs which greatly easies their fabrication by tilted dopant implantation using the high-k/metal gate as a shadow mask and dopant segregation. Two methods of dopant segregation are compared: Dopant segregation based on the “snow-plough” effect of dopants during silicidation and implantation into the silicide (IIS) followed by thermal outdiffusion. High drive currents of up to 60 μA/μm of planar p-TFETs were achieved indicating good silicide/silicon tunneling junctions. The non linear temperature dependence of the inverse subthreshold slope S indicates typical TFET behavior. Strained Si NW array n-TFETs with omega shaped HfO2/TiN gates showed high drive currents of 7 μA/μm @ 1V Vdd and steep inverse subthreshold slopes with minimum values of 50mV/dec due to the smaller band gap of strained Si and optimized electrostatics.

Hexagonal GdScO3: an epitaxial high-κ dielectric for GaN

GdScO3 was deposited by pulsed laser deposition on two different templates suitable for III-N growth: metalorganic vapour phase epitaxial GaN (0 0 0 1) on sapphire and molecular beam epitaxial Y2O3 on Si (1 1 1). The structure and crystallinity of the layers were determined as well as the band gap and permittivity of the material. It was found that GdScO3 grows epitaxially and crystallizes hexagonally in contrast to the usually found orthorhombic or amorphous phases. A band gap and permittivity κ of 5.2 eV and 24 were found, respectively, making GdScO3 a promising epitaxial gate dielectric for III-N transistor applications.