R. K. Nagaria

Performance analysis of high speed hybrid CMOS full adder circuits for low voltage VLSI design

This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC0.18 µm process models in Cadence Virtuoso Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.

Ultra low voltage high speed 1-bit CMOS adder

In this paper, we present a novel design for realize full adder circuit. Our approach based on XOR-XNOR design full adder circuits in a single unit. Objective of this work is to investigate the power, delay and power delay product of low voltage full adder cells in different CMOS logic styles. Simulation results illustrate the superiority of the proposed adder circuit against the conventional CMOS, Hybrid, Bridge, Xor-Xnor adder circuits in terms of power, delay, PDP. The bridge design style enjoys a high degree of regularity, higher density than conventional CMOS design style as well as lower power consumption, by using some transistors, named bridge transistors. The performance of the full adder circuits is based on GPDK 90nm CMOS process models at all range of the supply voltage starting from 0.65V to 1.5V evaluated by the comparison of the simulation results obtained from Cadence. Simulation results reveal that the proposed circuit exhibits lower PDP and is faster when compared with available 1-bit full adder circuits. To summarize, some performance criteria are considered in the design and evaluation of adder cells, of which some are at ease of design, robustness, silicon area, delay, and power consumption. The design is implemented on GDPK 90 nm process models in Cadence Virtuoso Schematic Composer at 1.5V single ended supply voltage and simulations are carried out on Spectre S.

Proposing a novel low-power high-speed mixed GDI Full Adder topology

This paper deals with the implementation of full adder chains by mixing different CMOS full adder topologies. The proposed approach is based on cascading fast Gate Diffusion Input (GDI) Full Adders interrupted by static gate having driving capability, such as inverter, thus exploiting the intrinsic low power consumption of such topologies. The results obtained show that the proposed mixed-topology approach based on GDI adders is capable of very low-power consumption and a very high-speed. This also enables a high degree of design freedom, given that the same (mixed) topology can be used for a wide range of applications. This greater flexibility also affords a significant reduction in the design effort. Delay and power has been evaluated by HSPICE simulation using TSMC 0.18µm CMOS technology considering minimum power design. The simulation results reveal better delay and power performance of proposed topology as compared to existing topologies at 1.8V supply voltage.

DFAL: Diode-Free Adiabatic Logic Circuits

The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been developed to explain the energy dissipation in the proposed circuit. Performance of the proposed logic is analyzed and compared with CMOS and reported adiabatic logic styles. Also the layout of proposed inverter circuit has been drawn. Subsequently proposed topology-based various logic gates, combinational and sequential circuits and multiplier circuit are designed and simulated. The simulations were performed by VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In proposed inverter the energy efficiency has been improved to almost 60% up to 100 MHz in comparison to conventional CMOS circuits. The present research provides low power high speed results up to 100 MHz, and proposal has proven to be used in power aware high-performance VLSI circuitry.

Leakage Power Analysis of Domino XOR Gate

Two new XOR gates are proposed. First proposed circuits adopt hybrid transistor topology in the pull-down network with all transistors being low threshold voltages. A second proposed circuit adopts hybrid topology with dual threshold voltage transistors. Simulation parameters are measured at 25°C and 110°C. First proposed circuit reduces leakage power consumption up to 50% at 25°C and 58% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 14% as compared to standard N-type domino XOR gate. Similarly, second proposed circuit reduces leakage power consumption up to 73% at 25°C and 90% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 39% as compared to standard N-type domino XOR gate.

Link utilization in survivable WDM mesh network

Protection and restoration are two techniques used in designing survivable Wavelength-division-multiplexing (WDM) networks. In this paper we propose new simple integer linear program (ILP) formulations for commonly accepted techniques such as, node-link and link-path model to allocate working and spare capacity in WDM mesh networks. Primary and backup lightpath allocation model is implemented by using two techniques such as, shortest path routing (SPR) algorithm and link utilization (LU) algorithm. LU algorithm is implemented with a dynamic link weight variable. In the same way spare capacity requirement is calculated for link restoration and path restoration model. Routing and wavelength assignment (RWA) is solved by wavelength continuity constraint. Multiple traffic patterns are generated using Poissons distribution. Simulation results validate that LU algorithm reduces link overhead marginally compared to SPR algorithm. Simulation is performed on widely used NSF network. We have identified the crucial links which are frequently used for traffic distribution.

Comparative study of Double Gate SOI FinFET and trigate Bulk MOSFET structures

The impact of systematic variations on transistor performance is shown for the trigate Bulk MOSFET and Double Gate SOI FinFET. This paper compares the variations in threshold voltage, subthreshold swing and drain induced barrier lowering (DIBL) by varying physical dimensions (gate oxide thickness, channel width and channel length) of the devices mentioned above. It also compares the temperature profile of the devices along the channel length. The electrical characteristics and temperature profile of the devices were simulated with the help of Sentaurus TCAD. The results obtained from the simulation reveal that trigate bulk MOSFET is more scalable than double gate SOI FinFET and can be used for better yield and reliability.

Conditional Precharge Dynamic Buffer Circuit

ABSTRACT In this paper, footless domino logic buffer circuit is proposed. It minimizes redundant switching at the dynamic and the output nodes. This circuit passes propagation of precharge pulse to the dynamic node and avoids precharge pulse to the output node which saves power consumption. Simulation is done using 0.18μm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circuit and compared the results with existing circuits for different logic function, loading condition, clock frequency, temperature and power supply. For capacitance 500fF, our proposed circuit reduces power consumption by 72.69%, 26.35% and 24.03% as compared to standard footless domino, SP-Domino and SSPD techniques.

Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load

Abstract A novel approach is proposed and discussed for designing CMOS double-tail dynamic comparator using the bulk-driven method. The bulk-driven method proposed thus far for low-power circuits result in reduced transconductance. The proposed technique uses the gate driven method to drive the inputs with bulk-driven loads. For the proposed comparator, mathematical analysis of delay and offset due to mismatch is presented. Additionally, a new optimized architecture of control unit is proposed to control both, offset voltage and kickback noise. To verify the outcomes, it is simulated in SPECTRE at 0.8 V of the supply voltage at 45 nm CMOS technology node. The proposed comparator achieves over 87% reduction in latch delay and 27% reduction of energy consumption over a conventional design. Monte-Carlo simulation is done to obtain the offset voltage, the result shows that the offset voltage is reduced by 62% using optimization technique.

Capacity Utilization of Protecting WDM Optical Networks for Unicast and Multicast Traffic

With the extremely high volume of traffic carried on wavelength division multiplexing (WDM) networks, survivability becomes increasingly critical in managing high speed networks. In a WDM network, the failure of network element (i.e. fiber links, and cross connects) may cause the failure of several optical channels, thereby leading to large data loss. Here the different approaches are investigated to protect mesh based WDM optical networks for such failure and subsequently, a mathematical model for capacity utilization for unicast traffic is presented. In this paper survivable schemes, such as path protection/restoration and link protection/restoration are reviewed for unicast as well as for multicast traffic. In addition to the shared link risk group (SLRG) based shared path protection (SLRG-SPP) and SLRG-based shared link protections (SLRG-SLP) are also discussed. It is observed that, the shared-path protection is more efficient in terms of capacity utilization over dedicated-path protection schemes and shared-link protection schemes, for random traffic demands. For low optical cross connect (OXC) configuration time (10 ns) the shared-link protection, scheme, offers better protection-switching time than the path-protection scheme. Taking high OXC configuration time (10 ms), the dedicated-path protection scheme has a better protection-switching time than the shared-path and shared-link protection.