R.B.R. van Silfhout

Virtual Qualification of Moisture Induced Failures of Advanced Packages

This paper presents a combined numerical and experimental methodology for predicting and preventing moisture induced failures in encapsulated packages. Prevention of such failures can enable efficient and optimal pre-selection of materials, their interfaces and geometric design with respect to the desired resistance to moisture. This virtual qualification methodology is illustrated for a specific BGA package which showed 50% failures (broken stitch-bonds) during HAST testing due to excessive warpage and/or delamination of different interfaces. For three different material combinations the moisture diffusion during the HAST test is predicted and subsequently thermo-mechanical-moisture simulations are performed where the effects of hygro-swelling, vapor pressure, thermal expansion and delamination on the failure mechanisms are predicted. The comparison of the simulation results of the different molding compounds with the observations of HAST testing indicates that the developed methods and models can predict the observed trends.

Prediction of interfacial delamination in stacked IC structures using combined experimental and simulation methods

Abstract Interfacial delamination is an often-observed failure mode in multi-layered IC packaging structures, which will not only influence the yield of wafer processes, but also have direct impact on the packaging reliability. The difference in coefficient of thermal expansion, together with thermal and thermal–mechanical loading are the main driving forces for interfacial delamination. First of all, this type of delamination is considered as a mixed mode of failure at the material interfaces. Hence, at least two stress components are needed to predict its occurrence. However, due to the singular stress field at the interface, one could hardly obtain the correct stresses at the interface. Therefore, a combined experimental–numerical method is used to investigate the initiation and propagation of the interface delamination. The purpose of the experimental shear and tensile tests is to measure the critical loads, at which delamination initiates. Then, a Finite Element (FE) model is constructed to convert the critical load into critical failure data for further numerical investigation. The FE model is so constructed that it reproduces the geometrical configurations of the tests. Due to the singular stress distribution at the interface, the calculated local stresses will be both mesh and residual-stiffness dependent. The influences of the FE parameters on the interface stresses are studied. After that, a progressive failure approach is, in combination with a group of failure criteria and the estimated local critical stresses, applied to predict the initiation and propagation of the delamination between epoxy mould compound and the passivation layer in the Integrated Circuit (IC) for three different package structures. The present method and the obtained results are valuable to determine design rules for IC packaging structures.

On wire failures in micro-electronic packages

At present, over 95% of the manufactured packages are still being wire bonded. Due to the ongoing trend of miniaturalization, material changes, and cost reduction, wire bond related failures are becoming increasingly important. Different finite element techniques are explored to their ability to describe the thermomechanical behavior of the wire embedded in the electronic package. The developed nonlinear and parametric finite element models are able to predict the strong nonlinear behavior of wire failures and multi-failure mode interaction accurately and efficiently. It is found that both processing and testing environments as well as the occurrence of delamination strongly increase the risk for wire failures. Our results indicate that processing and testing influences are much less than those of the delamination. Combining the strengths of predictive modeling with simulation-based optimization methods, the optimal wire shape is obtained.

Prediction of back-end process-induced wafer warpage and experimental verification

During the back-end processes of wafer manufacturing, wafer warpage occurs due to the mismatch in thermal expansion coefficients of the various applied materials. Large wafer warpage is one of the root causes leading to process and product failures. Therefore, the ability to predict the back-end process induced wafer warpage is important to achieve an optimal IC design and back-end process. This paper presents our research results of prediction and experimental verification of back-end process-induced wafer warpage due to thin film deposition and temperature changes. Both analytical and FE (finite element) methods are used to develop predictive models of the identified important back-end processes. These two models are verified by conducting warpage measurements of specially designed test wafers. Comparisons between the predictions with experimental results show that the predicted history of stress and warpage during the studied back-end processes are qualitatively reliable.

On Wire Failures in Microelectronic Packages

At present, over 95% of the manufactured packages are still being wire-bonded. Due to the ongoing trend of miniaturization, material changes, and cost reduction, wire-bond-related failures are becoming increasingly important. Different finite-element (FE) techniques are explored for their ability to describe the thermomechanical behavior of the wire embedded in the electronic package. The developed nonlinear and parametric FE models are able to predict the strong nonlinear behavior of wire failures and multifailure-mode interaction accurately and efficiently. It is found that both processing and reliability-testing environments as well as the occurrence of delamination strongly increase the risk of wire failures. Our results indicate that processing and reliability-testing influences are much less than those of the delamination. Combining the strengths of predictive modeling with simulation-based optimization methods, the optimal wire-loop shape is obtained.

A numerical method for efficient failure modelling of three-dimensional bond pad structures

Thermo-mechanical reliability issues are major bottlenecks in the development of future microelectronic components. This is caused by the following technology and business trends: (1) increasing miniaturization, (2) introduction of new materials, (3) shorter time-to-market, (4) increasing design complexity and decreasing design margins, (5) shortened development and qualification times, (5) gap between technology and fundamental knowledge development [1]. It is now well established that for future CMOS-technologies (CMOS065 and beyond), low-k dielectric materials will be integrated in the back-end structures [2]. However, bad thermal and mechanical integrity as well as weak interfacial adhesion result in major thermo-mechanical reliability issues. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily induce cracking, delamination and chipping of the IC back-end structure when no appropriate development is performed [3]. The scope of this paper is on the development of numerical models that are able to predict the failure sensitivity of complex three-dimensional microelectronic components while taking into account the details at the local scale (i.e., the back-end structure) by means of a multi-scale method. The damage sensitivity is calculated by means of an enhanced version of the previously introduced area release energy (ARE) criterion. This enhancement results in an efficient and accurate prediction of the energy release rate (ERR) at a selected bimaterial interface in any location. Moreover, due to the two-scale approach, local details of the structure are readily taken into account. In order to evaluate the efficiency and accuracy of the proposed method, several two-dimensional and three-dimensional benchmarks will be simulated. Finally, the failure sensitivity of a three-dimensional back-end structure during a wire pull test is evaluated.

Prediction of crack growth in IC passivation layers

The aluminium interconnect structures of ICs consists of materials with a large difference in the coefficient of thermal expansion (CTE). The IC backend and packaging processes are characterized by many temperature differences that will generate thermo-mechanical stresses in these interconnect structures. The resulting stress levels can lead to crack propagation in the brittle dielectric and passivation layers. To investigate the sensitivity to crack propagation in these materials, finite element simulations are performed using a J-integral approach. The J-integral approach is used to predict the crack stability for different crack lengths, positions and directions. The obtained results with respect to critical initial cracks match with field observations in actual IC interconnect structures.

Efficient Damage Sensitivity Analysis of advanced Cu Low-k Bond Pad Structures Using Area Release Energy

This paper presents an efficient method to describe the damage sensitivity of three-dimensional multi-layered structures. The index that characterizes this failure sensitivity is an energy measure called the area release energy, which predicts the amount of energy that is released upon crack initiation at an arbitrary position along an interface. The benefits of the method are: (1) the criterion can be used as damage sensitivity indicator for complex three-dimensional structures; (2) the criterion is energy based, thus more accurate than stress-based criteria; (3) unlike fracture mechanics, no initial defect size and location has to be assumed a priori. For the development of state-of-the-art CMOS technologies, the integration and introduction of low-k materials are one of the major bottlenecks due to their bad thermal and mechanical integrity and the inherited week interfacial adhesion. The use of ultra low-k (ULK) materials, such as porous dielectrics, will require significant development effort in order to result in reliable interconnect structures that are able to withstand the IC, packaging and assembly related thermo-mechanical and mechanical forces. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily result in cracking, delamination and chipping of the IC back-end structure if no appropriate measures are taken

Modelling methodology for linear elastic compound modelling versus visco-elastic compound modelling

Finite element (FE) simulations take an important place in predicting the thermo-mechanical plastic-package behaviour. Several studies in both industry and research cover this topic since the mechanical impact of the epoxy moulding compound (EMC) behaviour is of major impact on package reliability and the understanding of the material behaviour is limited. In the history of package modelling, large differences in thermo-mechanical stresses are found between (temperature dependent) elastic calculations and time dependent calculations, such as visco-elastic calculations. Visco-elastic compound behaviour is often recommended to take into account to predict stresses reliably, but takes significant effort and time for material characterization. In this paper the origin of stress differences was analyzed for different EMC material models in different realistic process conditions. By understanding the impact of realistic compound behaviour during real process conditions, an effective modelling approach was proposed which took less material characterisation and less calculation time. The modelling method was applied on a package simulation analyzing 3 different compounds and is verified by visco-elastic simulations.

Reliability of wirebonds in micro‐electronic packages

Purpose – At present, over 95 percent of the manufactured packages are still being wire bonded. Owing to the ongoing trend of miniaturization, material changes, and cost reduction, wire bond‐related failures are becoming increasingly important. This paper aims to understand these kinds of failures.Design/methodology/approach – Different finite element (FE) techniques are explored to their ability to describe the thermo‐mechanical behavior of the wire embedded in the electronic package. The developed nonlinear and parametric FE models are able to predict the strong nonlinear behavior of wire failures and multi‐failure mode interaction accurately and efficiently.Findings – It is found that both processing and testing environments as well as the occurrence of delamination strongly increase the risk for wire failures. The results indicate that processing and testing influences are much less than those of the delamination.Practical implications – Package designers should focus on limiting the occurrence of del...