R. Bates

Performance of an energy resolving X-ray pixel detector

We have built a back-illuminated, silicon X-ray detector with 16×16 pixels. This is bump-bonded to an integrated circuit containing a corresponding array of pre-amplifiers. The bump-bonded unit is wire bonded to two 128 channel integrated circuits which have signal shaping, peak-hold and sparcification logic. These integrated circuits output the analogue value of the individual X-ray and the address of the 300 μm×300 μm pixel. The system has previously demonstrated X-ray spectroscopy measurement in the 5–40 keV range with a resolution of 1 keV FWHM. This paper describes the performance of the system used in an X-ray diffraction experiment performed on the Daresbury Synchrotron Radiation Source. The second part demonstrates the successful operation of this pixellated detector for spectroscopy. In this part, the variation among the pixel outputs is accounted for without significantly affecting the noise performance.

Technology development of 3D detectors for medical imaging

Fabrication routes to realising ‘3D’ detectors in gallium arsenide have been investigated and their electrical characteristics measured. The geometry of the detector is hexagonal with a central anode surrounded by six cathode contacts. This geometry gives a uniform electric field with the maximum drift and depletion distance set by electrode spacings rather than detector thickness. The advantages of this structure include short collection distances, fast collection times and low depletion voltages depending on the electrode diameter and pitch chosen. These characteristics are fundamental for the application of 3D detectors in, for example, medical imaging and protein crystallography.

Edge pixel response studies of edgeless silicon sensor technology for pixellated imaging detectors

Silicon sensor technologies with reduced dead area at the sensors perimeter are under development at a number of institutes. Several fabrication methods for sensors which are sensitive close to the physical edge of the device are under investigation utilising techniques such as active-edges, passivated edges and current-terminating rings. Such technologies offer the goal of a seamlessly tiled detection surface with minimum dead space between the individual modules. In order to quantify the performance of different geometries and different bulk and implant types, characterisation of several sensors fabricated using active-edge technology were performed at the B16 beam line of the Diamond Light Source. The sensors were fabricated by VTT and bump-bonded to Timepix ROICs. They were 100 and 200 μ m thick sensors, with the last pixel-to-edge distance of either 50 or 100 μ m. The sensors were fabricated as either n-on-n or n-on-p type devices. Using 15 keV monochromatic X-rays with a beam spot of 2.5 μ m, the performance at the outer edge and corners pixels of the sensors was evaluated at three bias voltages. The results indicate a significant change in the charge collection properties between the edge and 5th (up to 275 μ m) from edge pixel for the 200 μ m thick n-on-n sensor. The edge pixel performance of the 100 μ m thick n-on-p sensors is affected only for the last two pixels (up to 110 μ m) subject to biasing conditions. Imaging characteristics of all sensor types investigated are stable over time and the non-uniformities can be minimised by flat-field corrections. The results from the synchrotron tests combined with lab measurements are presented along with an explanation of the observed effects.

3-D GaAs radiation detectors

A novel type of GaAs radiation detector featuring a 3-D array of electrodes that penetrate through the detector bulk is described. The development of the technology to fabricate such a detector is presented along with electrical and radiation source tests. Simulations of the electrical characteristics are given for detectors of various dimensions. Laser drilling, wet chemical etching and metal evaporation were used to create a cell array of nine electrodes, each with a diameter of 60 μm and a pitch of 210 μm. Electrical measurements showed I–V characteristics with low leakage currents and high breakdown voltages. The forward and reverse I–V measurements showed asymmetrical characteristics, which are not seen in planar diodes. Spectra were obtained using alpha particle illumination. A charge collection efficiency of 50% and a S/N ratio of 3 : 1 were obtained. Simulations using the MEDICI software package were performed on cells with various dimensions and were comparable with experimental results. Simulations of a nine-electrode cell with 10 μm electrodes with a 25 μm pitch were also performed. The I–V characteristics again showed a high breakdown voltage with a low leakage current but also showed a full depletion voltage of just 8 V.

The simulation of charge sharing in semiconductor X-ray pixel detectors

Two simulation packages were used to model the sharing of charge, due to the scattering and diffusion of carriers, between adjacent pixel elements in semiconductors X-ray detectors. The X-ray interaction and the consequent multiple scattering was modelled with the aid of the Monte Carlo package, MCNP. The resultant deposited charge distribution was then used to create the charge cloud profile in the finite element semiconductor simulation code MEDICI. The analysis of the current pulses induced on pixel electrodes for varying photon energies was performed for a GaAs pixel detector. For a pixel pitch of 25 μm, the charge lost to a neighbouring pixel was observed to be constant, at 0.6%, through the energies simulated. Ultimately, a fundamental limit on the pixel element size for imaging and spectroscopic devices may be set due to these key physical principles.

Thin hybrid pixel assembly with backside compensation layer on ROIC

The entire ATLAS inner tracking system will be replaced for operation at the HL-LHC . This will include a significantly larger pixel detector of approximately 15 m2. For this project, it is critical to reduce the mass of the hybrid pixel modules and this requires thinning both the sensor and readout chips to about 150 micrometres each. The thinning of the silicon chips leads to low bump yield for SnAg bumps due to bad co-planarity of the two chips at the solder reflow stage creating dead zones within the pixel array. In the case of the ATLAS FEI4 pixel readout chip thinned to 100 micrometres, the chip is concave, with the front side in compression, with a bow of +100 micrometres at room temperature which varies to a bow of −175 micrometres at the SnAg solder reflow temperature, caused by the CTE mismatch between the materials in the CMOS stack and the silicon substrate. A new wafer level process to address the issue of low bump yield be controlling the chip bow has been developed. A back-side dielectric and metal stack of SiN and Al:Si has been deposited on the readout chip wafer to dynamically compensate the stress of the front side stack. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach which is under development for this chip. It is demonstrated that the amplitude of the correction can be manipulated by the deposition conditions and thickness of the SiN/Al:Si stack. The bow magnitude over the temperature range for the best sample to date is reduced by almost a factor of 4 and the sign of the bow (shape of the die) remains constant. Further development of the backside deposition conditions is on-going with the target of close to zero bow at the solder reflow temperature and a minimal bow magnitude throughout the temperature range. Assemblies produced from FEI4 readout wafers thinned to 100 micrometres with the backside compensation layer have been made for the first time and demonstrate bond yields close to 100%.