T. McMullen

Edge pixel response studies of edgeless silicon sensor technology for pixellated imaging detectors

Silicon sensor technologies with reduced dead area at the sensors perimeter are under development at a number of institutes. Several fabrication methods for sensors which are sensitive close to the physical edge of the device are under investigation utilising techniques such as active-edges, passivated edges and current-terminating rings. Such technologies offer the goal of a seamlessly tiled detection surface with minimum dead space between the individual modules. In order to quantify the performance of different geometries and different bulk and implant types, characterisation of several sensors fabricated using active-edge technology were performed at the B16 beam line of the Diamond Light Source. The sensors were fabricated by VTT and bump-bonded to Timepix ROICs. They were 100 and 200 μ m thick sensors, with the last pixel-to-edge distance of either 50 or 100 μ m. The sensors were fabricated as either n-on-n or n-on-p type devices. Using 15 keV monochromatic X-rays with a beam spot of 2.5 μ m, the performance at the outer edge and corners pixels of the sensors was evaluated at three bias voltages. The results indicate a significant change in the charge collection properties between the edge and 5th (up to 275 μ m) from edge pixel for the 200 μ m thick n-on-n sensor. The edge pixel performance of the 100 μ m thick n-on-p sensors is affected only for the last two pixels (up to 110 μ m) subject to biasing conditions. Imaging characteristics of all sensor types investigated are stable over time and the non-uniformities can be minimised by flat-field corrections. The results from the synchrotron tests combined with lab measurements are presented along with an explanation of the observed effects.

Thin hybrid pixel assembly with backside compensation layer on ROIC

The entire ATLAS inner tracking system will be replaced for operation at the HL-LHC . This will include a significantly larger pixel detector of approximately 15 m2. For this project, it is critical to reduce the mass of the hybrid pixel modules and this requires thinning both the sensor and readout chips to about 150 micrometres each. The thinning of the silicon chips leads to low bump yield for SnAg bumps due to bad co-planarity of the two chips at the solder reflow stage creating dead zones within the pixel array. In the case of the ATLAS FEI4 pixel readout chip thinned to 100 micrometres, the chip is concave, with the front side in compression, with a bow of +100 micrometres at room temperature which varies to a bow of −175 micrometres at the SnAg solder reflow temperature, caused by the CTE mismatch between the materials in the CMOS stack and the silicon substrate. A new wafer level process to address the issue of low bump yield be controlling the chip bow has been developed. A back-side dielectric and metal stack of SiN and Al:Si has been deposited on the readout chip wafer to dynamically compensate the stress of the front side stack. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach which is under development for this chip. It is demonstrated that the amplitude of the correction can be manipulated by the deposition conditions and thickness of the SiN/Al:Si stack. The bow magnitude over the temperature range for the best sample to date is reduced by almost a factor of 4 and the sign of the bow (shape of the die) remains constant. Further development of the backside deposition conditions is on-going with the target of close to zero bow at the solder reflow temperature and a minimal bow magnitude throughout the temperature range. Assemblies produced from FEI4 readout wafers thinned to 100 micrometres with the backside compensation layer have been made for the first time and demonstrate bond yields close to 100%.