J. Ashby

Low Gain Avalanche Detectors (LGAD) for particle physics and synchrotron applications

A new avalanche silicon detector concept is introduced with a low gain in the region of ten, known as a Low Gain Avalanche Detector, LGAD. The detectors characteristics are simulated via a full process simulation to obtain the required doping profiles which demonstrate the desired operational characteristics of high breakdown voltage (500 V) and a gain of 10 at 200 V reverse bias for X-ray detection. The first low gain avalanche detectors fabricated by Micron Semiconductor Ltd are presented. The doping profiles of the multiplication junctions were measured with SIMS and reproduced by simulating the full fabrication process which enabled further development of the manufacturing process. The detectors are 300 μm thick p-type silicon with a resistivity of 8.5 kΩcm, which fully depletes at 116 V. The current characteristics are presented and demonstrate breakdown voltages in excess of 500 V and a current density of 40 to 100 nAcm−2 before breakdown measured at 20oC. The gain of the LGAD has been measured with a red laser (660 nm) and shown to be between 9 and 12 for an external bias voltage range from 150 V to 300 V.

Thin hybrid pixel assembly with backside compensation layer on ROIC

The entire ATLAS inner tracking system will be replaced for operation at the HL-LHC . This will include a significantly larger pixel detector of approximately 15 m2. For this project, it is critical to reduce the mass of the hybrid pixel modules and this requires thinning both the sensor and readout chips to about 150 micrometres each. The thinning of the silicon chips leads to low bump yield for SnAg bumps due to bad co-planarity of the two chips at the solder reflow stage creating dead zones within the pixel array. In the case of the ATLAS FEI4 pixel readout chip thinned to 100 micrometres, the chip is concave, with the front side in compression, with a bow of +100 micrometres at room temperature which varies to a bow of −175 micrometres at the SnAg solder reflow temperature, caused by the CTE mismatch between the materials in the CMOS stack and the silicon substrate. A new wafer level process to address the issue of low bump yield be controlling the chip bow has been developed. A back-side dielectric and metal stack of SiN and Al:Si has been deposited on the readout chip wafer to dynamically compensate the stress of the front side stack. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach which is under development for this chip. It is demonstrated that the amplitude of the correction can be manipulated by the deposition conditions and thickness of the SiN/Al:Si stack. The bow magnitude over the temperature range for the best sample to date is reduced by almost a factor of 4 and the sign of the bow (shape of the die) remains constant. Further development of the backside deposition conditions is on-going with the target of close to zero bow at the solder reflow temperature and a minimal bow magnitude throughout the temperature range. Assemblies produced from FEI4 readout wafers thinned to 100 micrometres with the backside compensation layer have been made for the first time and demonstrate bond yields close to 100%.