R. Dinapoli

Pixel readout electronics development for the ALICE pixel vertex and LHCb RICH detector

The ALICE1LHCB pixel readout chip emerged from previous experience at CERN. The RD-19 collaboration provided the basis for the installation of a pixel system in the WA97 and NA57 experiments. Operation in these experiments was key in the understanding of the system issues. In parallel the RD-49 collaboration provided the basis to obtain radiation tolerance in commercial submicron CMOS through special circuit layout. The new ALICE1LHB chip was developed to serve two different applications: particle tracking in the ALICE Silicon Pixel Detector and particle identification in the LHCb Ring Imaging Cherenkov detector. To satisfy the different needs for these two experiments, the chip can be operated in two different modes. In tracking mode all the 50 μm×425 μm pixel cells in the 256×32 array are read out individually, whilst in particle identification mode they are combined in groups of 8 to form a 32×32 array of 400 μm×425 μm cells. The circuit is currently being manufactured in a commercial 0.25 μm CMOS technology.

Pixel readout chips in deep submicron CMOS for ALICE and LHCb tolerant to 10 Mrad and beyond

The ALICE1LHCB chip is a mixed-mode integrated circuit designed to read out silicon pixel detectors for two different applications: particle tracking in the ALICE Silicon Pixel Detector and particle identification in the LHCb Ring Imaging Cherenkov detector. To satisfy the different needs for these two experiments, the chip can be operated in two different modes. In tracking mode all the 50 μm×425 μm pixel cells in the 256×32 array are read out individually, whilst in particle identification mode they are combined in groups of 8 to form a 32×32 array of 400 μm×425 μm cells. Radiation tolerance was enhanced through special circuit layout. Sensitivity to coupling of digital signals into the analog front end was minimized. System issues such as testability and uniformity further constrained the design. The circuit is currently being manufactured in a commercial 0.25 μm CMOS technology.

First results from the ALICE silicon pixel detector prototype

Abstract System prototyping of the ALICE silicon pixel detector (SPD) is well underway. The ALICE SPD consists of two barrel layers with 9.83 million channels in total. These are read out by the ALICE1LHCb pixel chip, which has been developed in a commercial 0.25 μm process with radiation hardening by design layout. The readout chip contains 8192 pixel cells each with a fast analog preamplifier and shaper followed by a discriminator and digital delay lines. Test results show a pixel cell noise of about 110 electrons rms and a mean minimum threshold of about 1000 electrons rms before threshold fine tuning. Several readout chips have been flip-chip bonded to detectors using two different bump-bonding techniques (solder, indium). Results of radioactive source measurements of these assemblies are presented for 90 Sr and 55 Fe sources. Several chip-detector assemblies have been tested in a 150 GeV / c pion beam at CERN where an online efficiency of about 99% across a wide range of detector bias and threshold settings was observed. All preliminary investigations confirm the functionality of the chip and the chip-detector assemblies for the ALICE experiment.

The Alice silicon pixel detector

CERN European Organization for Nuclear Research, CH-1211 Geneva 23, Switzerland Universita degli Studi di Padova, I-35131, Padova, Italy Dipartimento IA di Fisica e Sez. INFN di Bari, I-70126,Bari,Italy Comenius University, SK-84215 Bratislava, Slovakia NIKHEF, National Institute for Nuclear Physics and High Energy Physics, 1098 SJ Amsterdam, The Netherlands Slovak Academy of Sciences, SK-04353, Kosice, Slovakia Universita di Roma I, La Sapienza, I-00185, Roma, Italy

The ALICE on-Detector pixel PILOT system-OPS

The on-detector electronics of the ALICE silicon pixel detector (nearly 10 million pixels) consists of 1,200 readout chips, bump-bonded to silicon sensors and mounted on the front-end bus, and of 120 control (PILOT) chips, mounted on a multi chip module (MCM) together with opto-electronic transceivers. The environment of the pixel detector is such that radiation tolerant components are required. The front-end chips are all ASICs designed in a commercial 0.25-micron CMOS technology using radiation hardening layout techniques. An 800 Mbit/s Glink-compatible serializer and laser diode driver, also designed in the same 0.25 micron process, is used to transmit data over an optical fibre to the control room where the actual data processing and event building are performed. We describe the system and report on the status of the PILOT system.

A front-end for silicon pixel detectors in ALICE and LHCb

A new front-end for a pixel detector readout chip was designed. A non-standard topology was used to achieve low noise and fast return to zero of the preamplifier to be immune to pile-up of subsequent input signals. This front-end has been implemented on a pixel detector readout chip developed in a commercial 0.25 μm CMOS technology for the ALICE and LHCb experiments. This technology proved to be radiation tolerant when special layout techniques are used, and provides sufficient density for these applications. The chip is a matrix of 32 columns each containing 256 readout cells. Each readout cell comprises this front-end and digital readout circuitry, and has a static power consumption of about 60 μW.

Irradiation and SPS Beam Tests of the Alice1LHCb Pixel Chip

The Alice1LHCb front-end chip [1,2] has been designed for the ALICE pixel and the LHCb RICH detectors. It is fabricated in a commercial 0.25 μm CMOS technology, with special design techniques to obtain radiation tolerance. The chip has been irradiated with low energy protons and heavy ions, to determine the cross-section for Single Event Upsets (SEU), and with X-rays to evaluate the sensitivity to total ionising dose. We report the results of those measurements. We also report preliminary results of measurements done with 150 GeV pions at the CERN SPS.

The ALICE Pixel Detector Readout Chip Test System

The ALICE experiment will require some 1200 Readout Chips for the construction of the Silicon Pixel Detector [1] and it has been estimated that approximately 3000 units will require testing. This paper describes the system that was developed for this task.

The silicon pixel detector (SPD) for the ALICE experiment

The ALICE silicon pixel detector (SPD) constitutes the two innermost layers of the inner tracking system (ITS). The basic building block of the SPD is the half-stave carrying two detector ladders. The half-stave is equipped with a multi-chip module (MCM) and an optical fibre link for control and readout. A 5-layer aluminium/polyimide bus ensures the distribution of power and signals on each half-stave. The half-staves are mounted on a light-weight carbon-fibre structure with an integrated evaporative cooling system. An overview of the SPD development and the current status of the construction are presented.

Integration and test of the ALICE SPD readout chain

The silicon pixel detector (SPD) is the innermost element of the ALICE inner tracking system (ITS). The on-detector electronic system consists of several ASICs in a commercial 0.25μm CMOS process (radiationhardened by design), a low-mass multi layer Kapton cable for power and signal distribution (pixel bus), and a multi-chip module that includes a custom designed, very compact optical transceiver. The control and readout data transmission is done via optical fibres. Prototypes of the full read-out chain have been produced and tested. Integration issues and test results are presented and discussed.