R.G. Bankras

C-V test structures for metal gate CMOS

Gate leakage has complicated the layout and measurement of C-V test structures. In this paper the impact of metal gate introduction to C-V test structure design is discussed. The metal gate allows for wider-gate structures and for the application of n/sup +/-/sup p-/ diffusion edges. We show, both theoretically and with experimental data, the impact of both design modifications on C-V measurement results.

Nanoscale topography-capacitance correlation in high-K films : Interface heterogeneity related electrical properties

Kelvin probe force microscopy in ultrahigh vacuum was used to study inhomogeneities of the contact potential difference (CPD) and differential capacitance of thin atomic layer deposited Al2O3 films. CPD fluctuations correlate equally strongly with the surface topography for deposition on hydrogen-terminated Si and thermal SiO2. The correlation of the differential capacitance with the topography clearly distinguishes films based on the starting surface. The lateral electrical homogeneity of these thin oxides depends crucially on their initial nucleation.