Guido T. Sasse

Record RF performance of standard 90 nm CMOS technology

We have optimized 3 key RF devices realized in standard logic 90 nm CMOS technology and report a record performance in terms of n-MOS maximum oscillation frequency f/sub max/ (280 GHz), varactor tuning range and varactor and inductor quality factor.

MOSFET Degradation Under RF Stress

We report on the degradation of MOS transistors under RF stress. Hot-carrier degradation, negative-bias temperature instability, and gate dielectric breakdown are investigated. The findings are compared to established voltage- and field-driven models. The experimental results indicate that the existing models are well applicable into the gigahertz range to describe the degradation of MOS transistors in an RF circuit. The probability of gate dielectric breakdown appears to reduce rapidly at such high stress frequencies, increasing the design margin for RF power circuits.

RF CMOS reliability simulations.

We present a simulation approach to assess the reliability of an RF CMOS circuit under user conditions, based on existing DC degradation models for gate-oxide breakdown and hot-carrier degradation. The simulator allows for lifetime prediction of circuits that can withstand multiple breakdown events. Simulation results show that three power amplifiers with comparable initial circuit performance show an astronomic difference in reliability. The tool thus proves to be an asset in the analog design process.

The Relation Between Degradation Under DC and RF Stress Conditions

In this paper, we develop a method to derive degradation formulas for time-varying stress from the formulas for the constant-bias case, discuss its limitations, and apply it to a set of radio-frequency (RF) stress experiments. First, we will give a new derivation of the well-known power-law case without invoking any specific physical degradation model. Next, we will show that this derivation can be generalized to the broader class of degradation functions of type g(f(Vi)·t). We will illustrate our work with an example of hot-carrier degradation in 45-nm n-channel metal-oxide-semiconductor field-effect transistors, where an accurate prediction of the measured lifetime under RF stress conditions is obtained from the measured degradation under direct-current stress.

Application and Evaluation of the RF Charge-Pumping Technique

In this paper, we will discuss the extendibility of the charge-pumping (CP) technique toward frequencies up to 4 GHz. Such high frequencies are attractive when a significant gate leakage current flows, obscuring the CP current at lower pumping frequencies. It is shown that using RF gate excitation, accurate CP curves can be obtained on MOS devices with a leakage current density exceeding 1 Aldrcm-2. A theoretical analysis of the trap response to RF gate voltage signals is presented, giving a clear insight on the benefits and limitations of the technique.

The hot carrier degradation rate under AC stress

In this work the methodology used for predicting hot carrier device degradation under AC stressing conditions is critically re-examined. Having an accurate method is a key prerequisite of developing useful tools for the reliability simulation of any circuit. It will be shown that existing methods are not generally applicable. A new, better applicable method is presented and verified with experimental data.

Methodology for performing RF reliability experiments on a generic test structure

This paper discusses a new technique developed for generating well defined RF large voltage swing signals for on wafer experiments. This technique can be employed for performing a broad range of different RF reliability experiments on one generic test structure. The frequency dependence of a gate-oxide wear out stress was investigated using this methodology for frequencies of up to 1 GHz.

An LDMOS hot carrier model for circuit reliability simulation

In this paper we present a model that can be used to calculate hot carrier degradation in LDMOS devices within a circuit reliability simulation environment. The model is suitable for both nLDMOS and pLDMOS devices. We show experimental evidence on the applicability of this model over a broad range of VGS and VDS biases as well as temperature.

Gate-capacitance extraction from RF C-V measurements [MOS device applications]

In this work, a full two-port analysis of an RF C-V measurement set-up is given. This two-port analysis gives insight on the limitations of the commonly used gate capacitance extraction, based on the Y/sub 11/ parameter of the device. It is shown that the parasitics of the device can disturb the extracted gate capacitance and a new extraction scheme, based on the Z-matrix, is introduced that eliminates the effect of these parasitics. Measurement results prove the validity of this new extraction scheme, under different conditions.

C-V test structures for metal gate CMOS

Gate leakage has complicated the layout and measurement of C-V test structures. In this paper the impact of metal gate introduction to C-V test structure design is discussed. The metal gate allows for wider-gate structures and for the application of n/sup +/-/sup p-/ diffusion edges. We show, both theoretically and with experimental data, the impact of both design modifications on C-V measurement results.