Ralph Mason

A toolset for construction of hybrid intelligent forecasting systems: application for water demand prediction

Abstract This paper presents the Intelligent Forecasters Construction Set (IFCS) which is a toolset for constructing forecasting applications. The toolset supports the intelligent techniques of fuzzy logic, artificial neural networks, knowledge-based and case-based reasoning. The developer can construct a forecasting application using rules, procedures and flow diagrams, which are organized into a hierarchy of workspaces. The modularity of the IFCS allows subsequent addition of other modules of intelligent techniques. The IFCS was used for developing a water demand forecasting system based on real-world data obtained from the City of Reginas water distribution system and Environment Canada. A utility demand prediction system developed with the IFCS system is useful for optimizing operation costs of water plants. Some water plants need to pay a flat rate for electricity, which is set depending on peak kilowatt demand. Hence, if the peak kilowatt demand can be reduced, the operating costs of the plant can be lessened (Jamieson RA et al. American Water Works Association Journal 1993;85:48–55). An energy management system needs a good estimate of future customer demand in order to find the optimal pumping schedules that can minimize the peak kilowatt demand. Since the IFCS supports developing multiple predictor models, modeling of data can be expedited. The benefits of using multiple modules of artificial neural networks for demand prediction are presented. The results from this approach are compared with a linear regression and a case-based reasoning program. The performance comparisons among the forecasters will be discussed.

A low latency architecture for computing multiplicative inverses and divisions in GF(2/sup m/)

A low latency architecture to compute the multiplicative inverse and division in a finite field GF (2/sup m/) is presented. Compared to other proposals with the same complexity, this circuit has lower latency and can be used in error-correction or cryptography to increase system throughput. This architecture takes advantage of the simplicity to computing powers (2/sup l/) of an element in the Galois Field. The inverse of an element is computed in two stages: power calculation and multiplication. A division can be performed using only one more multiplication in the inversion circuit.

A digitally tuned 1.1 GHz subharmonic injection-locked VCO in 0.18/spl mu/m CMOS

In this paper, a second-order digitally controlled oscillator, based on subharmonic injection locking, is presented. The prototype design is implemented in a 0.18 /spl mu/m standard CMOS process. The implemented injection-locked oscillator, with a resonant frequency of 1.1 GHz, provides a low phase noise of -99.7 dBc/Hz at a 50 KHz offset. The oscillator is injection-locked with the eleventh harmonic of a low frequency 100 MHz PLL. Using switched-capacitor banks, the oscillator can be digitally tuned to within 300 KHz of the injection locking frequency which allows it to be locked with an input signal as low as - 53 dBm. The oscillator has an overall tuning range of 20% and together with an input amplifier consumes only 688 /spl mu/W when powered by a single 1.6V supply voltage.

A 0.18/spl mu/m CMOS, high Q-enhanced bandpass filter with direct digital tuning

A Q-enhanced filter is presented which operates at a high Q and employs sub-sampling and direct digital tuning. The filter is suitable as an IF filter in applications such as Bluetooth or GPS. The filter operates from 1.2V - 1.8V and consumes 1.08 mW at 500MHz with a SFDR of 37 dB and a Q of 650, at 1.5V.

Mapping hierarchical neural networks to VLSI hardware

Abstract Electronic ANNs rely heavily on the use of two-dimensional silicon and PCB substrates. Use of these substrates results in hierarchical hardware that exhibits varying levels of connectivity. Numerous approaches have been developed for generating hierarchical neural networks, however, generating hierarchical networks is only part of the problem. Equally important is the task of mapping hierarchical networks onto the hierarchical hardware. It will be shown theoretically and experimentally that, at least within a restricted domain, hierarchical networks can be mapped to hierarchical hardware more efficiently than nonhierarchical networks. The experimental hypothesis will be carried out through simulations with a number of clustering algorithms that rely on graph partitioning information. The clustering algorithms will also serve as a general purpose hierarchical hardware mapping tool. Their performance will be evaluated with both hierarchical and nonhierarchical test cases that include a MAXNET (pick maximum of inputs) application and a speech recognition task.

Application of Subharmonic Injection Locking of LC Oscillators to LO-Based Phase-Shifting Phased-Array Architectures

A ninth-subharmonic injection-locking scheme is proposed for local oscillator (LO) phase-shifting-based phased-array architectures operating in the ISM band at 24 GHz. The presented architecture employs a phase-shifter at the ninth subharmonic, a high-speed regenerative comparator, and a negative-gm oscillator to synthesize multiple phases of ninth-harmonic LO signals from a 2.41-GHz reference at the destination and in close proximity to the RF/millimeter-wave front-end mixers with first LO at 21.69 GHz. A digital phase-shift calibration technique is discussed. The reported LO phase-shifting and synthesis scheme is implemented in IBMs 130-nm CMOS technology and consumes a total of 32 mA per LO element from a 1.2-V supply. The injection-locked oscillators have a phase-noise performance of - 107.17 dBc/Hz at 1-MHz offset from 21.51 GHz. The maximum phase-shift error at 21.69 GHz is 9.86° and 2.1° before and after calibration, respectively.

Analog DFT using an undersampling technique

This article presents a novel approach to analog design for test (DFT). The approach is based on wideband undersampling techniques using multiple samplers on-chip. Using this technique, signals being tested can be mixed down to lower frequencies before being brought off-chip.

A differential bipolar quasi-passive cyclic digital-to-analog converter with 4.416 MSps conversion rate and -77 dB THD

Cyclic Digital-to-Analog Converters (DACs) can provide low power alternatives to current steering DACs for medium conversion rates. A cyclic DAC capable of achieving lite-rate DSL performance for downstream is presented in this paper. With the help of a differential bipolar architecture, the DAC delivers close to 12 bits of linearity at 4.416 MS/s conversion rate. The cyclic D/A converter, implemented in a 0.35-/spl mu/m double-poly CMOS technology, dissipates only 10 mW.

CMOS LNA in wireless applications

A 1.9 GHz low noise amplifier has been designed in a standard CMOS .35 micron process. The amplifier provides a gain of 21 dB with a noise figure only 1.4 dB while drawing 6.5 mW from a 1.5 V supply. The design process and simulation results are presented. The LNA design with variable bias is suitable for the proposed smart receiver.

Complete SOC Transceiver in 0.18

Portable audio products have not yet seen a wireless headphone solution that has been widely accepted. The main reason for this is that power consumption for current solutions is too high. We present a solution the uses a sub-sampling receiver combined with Q-enhanced RF filtering and injection-locked LO generation to provide high performance with low power consumption. This paper describes in detail the transceiver architecture, frequency plan, tuning algorithms and obtained performance. The transceiver is fabricated in TSMC 0.18 μm CMOS. The analog and RF sections of the transceiver consume peak currents of 5.2 mA in RX mode and 20.3 mA in TX mode.