Subodh Wairya

Performance analysis of high speed hybrid CMOS full adder circuits for low voltage VLSI design

This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC0.18 µm process models in Cadence Virtuoso Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.

Ultra low voltage high speed 1-bit CMOS adder

In this paper, we present a novel design for realize full adder circuit. Our approach based on XOR-XNOR design full adder circuits in a single unit. Objective of this work is to investigate the power, delay and power delay product of low voltage full adder cells in different CMOS logic styles. Simulation results illustrate the superiority of the proposed adder circuit against the conventional CMOS, Hybrid, Bridge, Xor-Xnor adder circuits in terms of power, delay, PDP. The bridge design style enjoys a high degree of regularity, higher density than conventional CMOS design style as well as lower power consumption, by using some transistors, named bridge transistors. The performance of the full adder circuits is based on GPDK 90nm CMOS process models at all range of the supply voltage starting from 0.65V to 1.5V evaluated by the comparison of the simulation results obtained from Cadence. Simulation results reveal that the proposed circuit exhibits lower PDP and is faster when compared with available 1-bit full adder circuits. To summarize, some performance criteria are considered in the design and evaluation of adder cells, of which some are at ease of design, robustness, silicon area, delay, and power consumption. The design is implemented on GDPK 90 nm process models in Cadence Virtuoso Schematic Composer at 1.5V single ended supply voltage and simulations are carried out on Spectre S.

Optimized Approach for Reversible Code Converters Using Quantum Dot Cellular Automata

Reversible logic has gained importance in the present development of low-power and high-speed digital systems in nanotechnology. In this manuscript, we have introduced and optimized the reversible Binary to Gray and Gray to Binary code converters circuit using two new types of reversible gates. Two new types of 3 × 3 reversible gates, namely BG-1 gate (Binary to Gray) and GB-1 gate (Gray to Binary), have been proposed to design converter circuits without any garbage outputs. In addition, useful theorems have been developed, associated with the number of gates, garbage outputs, constant input and quantum cost of the reversible converters. The QCA Designer v2.0.3 tool is used for simulation to test the workability of reversible code converters. The simulation results show that the design works correctly and extracted parameters are better than the previously reported designs. Area and lower bound parameter analysis also show that the design is based on the optimized approach.

An inventive design of 4*4 bit reversible NS gate

The model of computing in which the computational progression is reversible or to some extent time inverting is entitled reversible computing. In the modern epoch reversible logic has materialized as a promising, competent technology comprising its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The conventional gates such as AND, OR, and EXOR are not reversible. Here in this manuscript we put forward a 4*4 reversible gate design called “NSG”. The most noteworthy, considerable attribute of the proposed gate is that it can work individually as a reversible full adder, reversible full subtractor, reversible half adder, and reversible half subtractor. That is now we are capable of implementing reversible full adder, subtractor and reversible half adder, subtractor with a single gate only. The proposition of this meticulous manuscript is a design a parity preservation property using NS Gate.

Testable Novel Parity-Preserving Reversible Gate and Low-Cost Quantum Decoder Design in 1D Molecular-QCA

In this era of emerging technology, reversible logic is applied for circuit design. Due to the deep submicron and scaling, a number of pitfalls are faced by the CMOS technology. So a lot of constraints related to CMOS are stated with the QCA technology. The aim of this paper is the efficient conservative reversible decoder circuit design with optimal reversible metrics. It aims at furnishing a proposed DC gate (DC stands for decoder comparator) to help the construction of these mentioned circuits. Finally, the DC is employed to construct the n-bit reversible decoder. Moreover, a new concept of the quantum equivalent of combined reversible gates is presented by the algorithm. By the comparative outcomes, it is found that the proposed decoder had achieved 25% quantum cost, 66% gate count, and 50% garbage outputs as compared to the counterpart. Further, stuck-at-fault for the single- and multiple-bit input and output is applied to the DC gate for testability. Moreover, the DC gate in the physical foreground ...

Approach to design a high performance fault-tolerant reversible ALU

In the digital circuit design, the primary factors are low power and a high packing density. The reversible logic circuit in quantum-dot cellular automata (QCA) framework is hoped to be effective in addressing the factor of power consumption at nanoscale regime. Fault tolerant circuits are suited of interruption of errors at the outputs. This manuscript focuses the design of ALU in QCA-based and propose new parity preserving gate. It has been introduced that new reversible gate, namely, universal parity preserving gate (UPPG), to optimise the ALU circuits. An algorithm and lemmas are shown in designing ALU. The ALU generates a number of arithmetic and logical function with using only less architectural complexity. Most importantly circuit design focuses on optimising the gate count and quantum cost. In addition to optimisation, the workability of UPPG gate is tested by QCA and the simulation result obtained ensures the correctness of the design.

Evolution of structure of some binary group based n bit comparator, n-to-2n decoder by reversible technique.

Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI circuit design. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2- bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n decoder. Different proposed novel reversible circuit design style is compared with the existing ones. The relative results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms the present design style in terms of number of gates, garbage outputs and constant input.

Novel conservative reversible error control circuits based on molecular QCA

Quantum-dot cellular automata are a prominent part of the nanoscale regime. They use a quantum cellular based architecture which enables rapid information process with high device density. This paper targets the two kinds of novel error control circuits such as Hamming code, parity generator and checker. To design the HG-PP (HG = Hamming gate, PP = parity preserving), NG-PP (NG = new gate) are proposed for optimising the circuits. Based on the proposed gates and a few existing gates, the Hamming code and parity generator and checker circuits are constructed. The proposed gates have been framed and verified in QCA. The simulation outcomes signify that their framed circuits are faultless. In addition to verification, physical reversible is done. The reversible major metrics such as gate count, quantum cost, unit delay, and garbage outputs, uses best optimisation results compared to counterparts. They can be utilised as a low power error control circuit applied in future communication systems.

ON THE NEW DESIGN OF SINUSOID VOLTAGE CONTROLLED OSCILLATORS USING MULTIPLIER IN CFA-BASED DOUBLE INTEGRATOR LOOP

The design and analysis of some new voltage controlled oscillators with sinewave output are proposed. The configurations are based on the implementation of double-integrator loop (DIL) using the Current Feedback Amplifier (CFA) device. For voltage control of the time constants of the DIL, the ICL-8013 multiplier element has been appropriately utilized in a feedforward/feedback connection within the loop. The oscillation frequency (ωo) is tunable by the d.c. control voltage (Vc) of the multiplier. The active ωo-sensitivity relative to the CFA port errors (e) is quite low. The VCO practical performance had been tested both with hardware implementation and with PSPICE macromodel simulation, in a typical frequency range of 50 KHz–1.5 MHz.

A Novel Parity Preserving Reversible Binary-to-BCD Code Converter with Testability of Building Blocks in Quantum Circuit

The reversible logic circuit is popular due to its quantum gates involved where quantum gates are reversible and noted down feature of no information loss. In this paper, parity preserving reversible binary-to-BCD code converter is designed, and effect of reversible metrics is analyzed such as gate count, ancilla input, garbage output, and quantum cost. This design can build blocks of basic existing parity preserving reversible gates. The building blocks of the code converter reversible circuit constructed on Toffoli gate based as well as elemental gate based such as CNOT, C-V, and C-V+ gates. In addition, qubit transition analysis of the quantum circuit in the regime of quantum computing has been presented. The heuristic approach has been developed in quantum circuit construction and the optimized quantum cost for the circuit of binary-to-BCD code converter. Logic functions validate the development of quantum circuit. Moving the testability aim are figured in the quantum logic circuit testing such as single missing gate and single missing control point fault.