R. Laffont

A new floating gate compact model applied to flash memory cell

Abstract The aim of this work is to present a method developed to simulate the direct current and transient properties of the floating gate memories. This method includes metal oxide semi-conductor charge neutrality, charges stored into the floating gate, injection currents and metal oxide semi-conductor field effects transistor characteristics to determine the surface potential variation along the channel, the floating gate potential and as a result the drain current and the threshold voltage. The resulting model was implemented in a common circuit simulator, Eldo, and used to study the flash memory writing/erasing operations. Channel hot electron injection and classical Fowler–Nordheim currents are used respectively to program and to erase this kind of memory. The simulator validation is obtained by comparing transient threshold voltage measurements performed on 0.15 μm devices with simulations.

MM11 based flash memory cell model including characterization procedure

The objective of this paper is to present a flash cell model for static and transient simulations. As a core element of this model, a Philips MOS model (MM11) model has been used coupled with the charge neutrality expression in the structure. The charge neutrality, including the charge trapped in the floating gate, is applied to determine the potential of the floating gate. From the floating gate potential, related to the terminal voltages, the drain current and the different charges present in the cell structure are calculated with the MM11 formulation. This pragmatic model takes into account the different injection mechanism (CHE, CHISEL and FN). Moreover, the characterization procedure developed under ICCAP to extract the MM11 model card as well as the tunnel current parameters is presented. This model has been successfully implemented in ELDO

A new architecture of EEPROM for high density and high reliability application

A concept of dual-control gate EEPROM cell and array architecture are proposed. New programming conditions used for write and erase operations are developed to improve the lifetime of the cell. This approach allows a programming of the cell only by the top of the structure without bias on the drain-bulk or source-bulk junctions. Moreover, compared to the standard FLOTOX EEPROM, the select transistor has been eliminated, thus attaining a single transistor configuration so a high density memory cell. A compact model and 2D numerical simulation show that the basic functions of this cell, namely reading, programming and erasing are possible with a suitable setting of the applied voltages. Scalability and endurance potentiality make this cell interesting for future high-density and high reliability applications.

A new method to quantify retention-failed cells of an EEPROM CAST

The cell array stress test (CAST) is a very simple tool to study one of the main issues of Non Volatile Memory reliability: data retention. However, it is not possible to easily quantify and localise the retention-failed cells of a CAST. Thus, a new experimental technique to localize and to quantify retention-failed EEPROM cells into a CAST is presented in this paper. This new technique is based on light emission microscopy; the aim is to observe light emission coming from cells and to localize their position with accuracy on CAST area. It is a visual and non destructive method which validity has been shown on cycled cells after a retention test.

A new robust over rail to rail comparator based on DCG-FGT transistor

A new comparator based on Dual Control Gate Floating Gate Transistor (DCG-FGT) that allow increasing input voltage range over rail-to-rail is proposed. The comparator operates with a supply voltage ranging from 1.6V to 3.6 V in 90 nm CMOS technology. The comparator is simulated under ELDO and consumes 3.2μA under typical condition.

An evaluation of the extrinsic cells number in a memory array using cross-correlation products and deconvolution: an instance of a microelectronics experimental inverse problem

This work is devoted to a new, fast and efficient method of evaluating the number of marginal cells in a non-volatile electrical memory array. This extraction from experimental data is fundamentally an inverse problem. The method proposed here is based on simple cross-correlation functions and de-convoluting operations. With the microelectronics device dimension downscaling, the reliability of non-volatile electrical memory has become crucial and any marginal cell can compromise the functioning of the whole array (containing hundreds of thousands of elementary cells). A specific array called Cell Array Structure Test (CAST) has been developed as a useful characterization tool to statistically study retention and endurance performance with few experimental operations. However, this device cannot easily count the low number of failed cells among hundreds of thousands. That is why we had to develop a mathematical method to extract this major quantity from measurements. This method has been validated on an EEPROM CAST – 0.13 µm technology node, but it is extendable to all memory devices integrated in parallel array and more generally to any electrical measurement done in a similar configuration.

Effect of AC stress on oxide TDDB and trapped charge in interface states

This study is driven by the need to improve the oxide reliability of a memory cell. The effects of dynamic high electric field stressing on thin oxide have been studied. Difference between time to breakdown with static stress and dynamic stress has been shown. Trapped charge in interface states under dynamic and static oxide field stress has been investigated with quasi-static capacitance voltage measurement. The duty cycle of the dynamic stress has an important effect on the oxide lifetime. This duty cycle effect is also impacted by the electric field. Interface Hydrogen Released model have been studied to understand relaxation phenomena. Real use stress conditions show an important gain on lifetime.

Investigation of the effects of constant voltage stress on thin SiO2 layers using dynamic measurement protocols

In this work, thin oxide degradation resulting from constant voltage stress has been investigated. New experimental protocols have been set up to gather information about the nature and location of the electric charge trapped in the oxide during electric stress. Experimental results obtained from dynamic current and capacitance measurements evidence the simultaneous presence of charges trapped in the oxide bulk as well as interface traps at low electron injection. In particular, real-time monitoring of the screening of positive trapped charge by tunneling electrons and of the emptying of interface states has been achieved.

Determination of oxide properties with a new fast tunneling current measurement protocol

Written and erased states of a floating gate Non-Volatile Memory (NVM) cell are obtained by modulating the electric charge contained in its floating gate, which is realized by making electrons transit through the tunnel oxide thanks to Fowler-Nordheim (FN) conduction [1]. An accurate prediction of the ‘write’ and ‘erase’ threshold voltages requires good knowledge about the injection current, which is not an easy task when transient phenomena and oxide degradation are involved. Simple Fowler-Nordheim laws are not adequate to explain the shape of I-V characteristics, especially for positive drain voltages [2], as seen on figure 1, and deep depletion in the drain has been shown to have an impact on erase operations [3].

A 0.18 /spl mu/m flash source side erasing improvement

The aim of this work is to present two solutions developed to optimize Flash cell erasing time. These solutions have been proposed with our flash simulator based on Pao and Sah approach. This model was implemented in a common circuit simulator, Eldo, and used to study the Flash memory writing/erasing operations. Thank to simulations, we have proposed two solutions to increase injection efficiency of the cell during erasing operation. The first solution is based on signal optimization and the second on a simple process modification during SAS etching. These two solutions have been validated with ST-Microelectronics Flash technologies.