R. Oxland

Demonstration of scaled Ge p-channel FinFETs integrated on Si

We report the first demonstration of scaled Ge p-channel FinFET devices fabricated on a Si bulk FinFET baseline using the Aspect-Ratio-Trapping (ART) technique [1]. Excellent subthreshold characteristics (long-channel subthreshold swing SS=76mV/dec at 0.5V), good SCE control and high transconductance (1.2 mS/μm at 1V, 1.05 mS/μm at 0.5V) are achieved. The Ge FinFET presented in this work exhibits highest gm/SS at Vdd=1V reported for non-planar unstrained Ge pFETs to date.

An Ultralow-Resistance Ultrashallow Metallic Source/Drain Contact Scheme for III–V NMOS

We report an ultrashallow metallic source/drain (S/D) contact scheme for fully self-aligned III-V NMOS with specific contact resistivity and sheet resistance which, for the first time, demonstrate performance metrics that may be compatible with the ITRS R_ext requirements for 12-nm technology generation device pitch. The record specific contact resistivity between the contact pad and metallic S/D of ρ_c = 2.7 ·10^-9 Ω·cm² has been demonstrated for 10 nm undoped InAs channels by forming an ultrashallow crystalline ternary NiInAs phase with R_sh = 97 Ω/sq for a junction depth of 7 nm. The junction depth of the S/D scheme is highly controllable and atomically abrupt.

Scaled p-channel Ge FinFET with optimized gate stack and record performance integrated on 300mm Si wafers

We demonstrate scaled, replacement gate high-k/metal gate p-channel Ge FinFETs integrated onto 300mm Si wafers for which the best device shows record peak g_{m, ext}=2.7mS/μm (g_{m, int}=3.3mS/μm), Q (≡g_{m, ext}/SS_sat) = 32.4 and I_on= 497μA/μm at I_off = 100nA/μm, all at V_ds= -0.5V. The high performance is a result of successful integration of <;110> oriented, highly scaled Ge fins on silicon substrates and of a low D_it gate stack with capacitance equivalent thickness=8Å. This optimized gate stack supports the highest hole mobility ever reported at sub-10Å CET. Furthermore, Ge FinFETs in the present work outperform any other reported Ge devices by more than ~2.5× (g_m/SS metric) and ~2× (I_on/I_off metric) at shortest gate lengths (down to 20nm) to the best of our knowledge.

InAs hole inversion and bandgap interface state density of 2 x 10(11) cm(-2) eV(-1) at HfO2/InAs interfaces

High-k/InAs interfaces have been manufactured using InAs surface oxygen termination and low temperature atomic layer deposition of HfO2. Capacitance–voltage (C–V) curves revert to essentially classical shape revealing mobile carrier response in accumulation and depletion, hole inversion is observed, and predicted minority carrier response frequency in the hundred kHz range is experimentally confirmed; reference samples using conventional techniques show a trap dominated capacitance response. C–V curves have been fitted using advanced models including nonparabolicity and Fermi-Dirac distribution. For an equivalent oxide thickness of 1.3 nm, an interface state density Dit = 2.2 × 1011 cm−2 eV−1 has been obtained throughout the InAs bandgap.

Ge n-channel FinFET with optimized gate stack and contacts

Whilst high performance p-channel Ge MOSFETs have been demonstrated [1-4], Ge n-channel MOSFET drive current has been lagging behind mainly hampered by high access resistance and poor gate stack passivation [5-9]. In this work, we address these issues on a module level and demonstrate Ge enhancement mode nMOS FinFETs fabricated on 300mm Si wafers implementing optimized gate stack (D_it <; 2×10¹¹ eV^-1·cm^-2), n+-doping (Nd > 1×10²⁰ cm^-3) and metallization (ρ_c = 1×10^-7 Ωcm²) modules. L_G ~ 40 nm devices achieved I_on = 50 μA/μm at I_off = 100 nA/um, S ~ 124 mV/dec, at V_DD = 0.5V. The same gate stack and contacts were deployed on planar devices for reference. Both FinFET and planar devices in this work achieved the highest reported g_m/S_sat at 0.5 V to date for Ge nMOS enhancement mode transistors to the best of our knowledge at shortest gate lengths.

Field-Effect Mobility of InAs Surface Channel nMOSFET With Low

Frequency (100 Hz ≤ f ≤ 1 MHz) and temperature (-50 ≤ T 20 °C) characteristics of low interface state density D_it high-κ gate-stacks on n-InAs have been investigated. Capacitance-voltage (C-V) curves exhibit typical accumulation/depletion/inversion behavior with midgap D_it of 2 × 10¹¹ and 4 × 10¹¹ cm^-2 eV^-1 at -50 °C and 20 °C, respectively. Asymmetry of low-frequency C-V curves and C-T dependence for negative voltage showing a sharp transition of ≅-20 dB/decade between low- and high-frequency behavior indicate surface inversion. An inversion carrier activation energy and an InAs hole lifetime of 0.32 eV and 2 ns have been extracted, respectively. Surface channel nMOSFETs with gate length L_g = 1 μm, channel thickness = 10 nm, and equivalent oxide thickness (EOT) 1 ≤ EOT ≤ 1.6 nm have been fabricated. For EOT = 1 nm, a subthreshold swing S = 65 mV/decade, transconductance g_m = 1.6 mS/μm, and ON-current I_ON = 426 μA/μm at an OFF-current I_OFF = 100 nA/μm (supply voltage V_dd = 0.5 V) have been measured. Peak electron field-effect mobilities of 6000-7000 cm²/Vs at sheet electron densities of 2-3 × 10¹² cm^-2 were obtained for EOT as small as 1 nm.

D_{\rm it}

Record setting III-V MOSFETs are reported. For the first time performance better than state-of-the-art HEMTs is demonstrated. For a MOSFET with 10 nm unstrained InAs surface channel and L_g = 130 nm operating at 0.5 V, on-current as high as I_on = 601 μA/μm (at fixed I_off = 100 nA/μm) is achieved. This record performance is enabled by g_{m, ext} = 2.72 mS/μm and S = 85 mV/dec, DIBL = 40 mV/V, resulting from breakthroughs in epitaxy and III-V/dielectric interface engineering. Measured mobility is 7100 cm²/V.s at n_s = 6.7×10¹² cm^-2. Device simulations further elucidate the performance potential of III-V N-MOSFETs.

Scaled Gate-Stack

InAs nanowires (NW) grown by MOCVD with diameter d as small as 10 nm and gate-all-around (GAA) MOSFETs with d = 12-15 nm are demonstrated. I_on = 314 μA/μm, and S_sat =68 mV/dec was achieved at V_dd = 0.5 V (I_off = 0.1 μA/μm). Highest g_m measured is 2693 μS/μm. Device performance is enabled by small diameter and optimized high-k/InAs gate stack process. Device performance tradeoffs between g_m, R_on, and I_min are discussed.

InAs N-MOSFETs with record performance of I on = 600 μA/μm at I off = 100 nA/μm (V d = 0.5 V)

We report on the first realization of InAs n-channel gate-all-around nanowire MOSFETs on 300 mm Si substrates using a fully very large-scale integration (VLSI)-compatible flow. Scaling of the equivalent oxide thickness EOT in conjunction with high-κ dielectric engineering improves the device performance; with an optimized gate stack having an EOT of 1.0 nm, the sub-threshold swing S is 76.8 mV/dec., and the peak transconductance gm is 1.65 mS/μm, at V_ds of 0.5 V, for a gate-all-around nanowire MOSFET having a gate length L_g of 90 nm, a nanowire height H_NW of 25 nm, and a nanowire width W_NW of 20 nm, resulting in Q ≡ gm/S = 21.5, a record for InAs on silicon. Furthermore, we report a source/drain resistance R_sd of 160-200 Ω·μm, amongst the lowest values reported for III-V MOSFETs. Our VLSI-compatible process provides high device yield, which enables statistically reliable extraction of electron transport parameters, such as unidirectional thermal velocity vtx of 3-4×10⁷ cm/s and back-scattering coefficient r_c as a function of gate length.

InAs nanowire GAA n-MOSFETs with 12–15 nm diameter

The integration of III-V semiconductors on silicon (Si) substrate has been an active field of research for more than 30 years. Various approaches have been investigated, including growth of buffer layers to accommodate the lattice mismatch between the Si substrate and the III-V layer, Si- or Ge-on-insulator, epitaxial transfer methods, epitaxial lateral overgrowth, aspect-ratio-trapping techniques, and interfacial misfit array formation. However, manufacturing standards have not been met and significant levels of remaining defectivity, high cost, and complex integration schemes have hampered large scale commercial impact. Here we report on low cost, relaxed, atomically smooth, and surface undulation free lattice mismatched III-V epitaxial films grown in wide-fields of micrometer size on 300 mm Si(100) and (111) substrates. The crystallographic quality of the epitaxial film beyond a few atomic layers from the Si substrate is accomplished by formation of an interfacial misfit array. This development may enable future platforms of integrated low-power logic, power amplifiers, voltage controllers, and optoelectronics components.