R. S. Larsen

Microstore - The Stanford Analog Memory Unit

An NMOS device has been developed which provides high speed analog signal storage and readout for time expansion of transient signals. This device takes advantage of HMOS-1 VLSI technology to implement an array of 256 storage cells. Sequential samples of an input waveform can be taken every 5 ns while providing an effective sampling aperture time of less than 1 ns. The design signal-to-noise ratio is 1 part in 2000. Digital control circuitry is provided on the chip for controlling the read-in and read-out processes. A reference circuit is incorporated in the chip for first order compensation of leakage drifts, sampling pedestals, and temperature effects.

Overview of the Data Acquisition Electronics System Design for the SLAC Linear Collider Detector (SLD)

The SLD Detector will contain five major electronics subsystems: Vertex, Drift, Liquid Argon Calorimeter, Cerenkov Ring Imaging, and Warm Iron Calorimeter. To implement the approximately 170,000 channels of electronics, extensive miniaturization and heavy use of multiplexing techniques are required. Design criteria for each subsystem, overall system architecture, and the R & D program are described.

Drift Chamber and Pulse Height Readout Systems Using Analog Multiplexing

Drift chamber and pulse-height readout systems are being developed for use in a new large scale detector at the SPEAR colliding beam facility. The systems are based upon 32 channels of sample-and-hold together with an analog multiplexer in a single-width CAMAC module. The modules within each crate are scanned by an autonomous controller containing a single ADC and memory plus arithmetic capability for offset, gain and linearity corrections. The drift chamber module has a facility for extracting hit wire information for use in trigger decision circuitry.

Status of the Interlaboratory Development of a High-Speed Standard Data Bus - FASTBUS

The FASTBUS project is an interlaboratory effort to develop a next generation laboratory standard data bus. The principal design goals are high speed (<100 nsec per word block transfers), wide data path (32 bits), identical parallel addressing architectures at both system and sub-system levels, ability to support multiple parallel master controllers, and ability to support special modes of operation for high energy physics applications. The current status of development is briefly described.

Status of the FASTBUS Standard Data Bus

FASTBUS is a new laboratory standard data bus intended for use in experimental data acquisition and control. The development of FASTBUS began with a feasibility study in 1976 and is presently at the development prototyping stage. The principal aims of the standard are to provide a factor of ten or more improvement in speed of data transfers over present systems, as well as to provide an architecture for systems containing multiple processors. Developmental prototypes now in progress include crates, backplanes, cooling devices, power supplies, test and diagnostic modules, and user modules. A sizeable software development effort is also underway. Several experiments have made commitments to use FASTBUS. A review of current work and potential applications is given.

Interlaboratory Development of an Integrated Circuit for Multiwire Proportional Chambers

Progress has been made toward developing a special TTL hybrid integrated circuit for proportional wire chambers. Two manufacturers, Fairchild and Texas Instruments, both appear close to completing a satisfactory circuit. Deliveries of hybrid prototypes will require probably 6 to 8 weeks after final approval of the breadboards.

The CSI story: IEEE PES Community Solutions Initiative

The IEEE PES Community Solutions Initiative is dedicated to helping IEEE reach the Humanitarian Technology Challenge (HTC) -United Nations (UN) goal of achieving a major impact in global poverty reduction of which energy poverty is a major factor. The CSI vision emulates the goals of many like-minded groups of building bottom-up community prosperity through training and empowering local entrepreneurs to manage profitable businesses capable of growing to serve a million people in the first 5 years of operation. A successful business and technology model has been demonstrated at a seed funding level in Haiti and now is striving to attract further investment from both aid agencies and Social investment venture capitalists to expand marketing and production to full scale. The first initiative in Haiti is now three years old and new initiatives in Nigeria, Cameroon and South Sudan started in July 2012. In addition, CSI with a growing list of partners is dedicated to leveraging basic electricity to support a variety of uses including interconnectivity and interactive web-based affordable education at many levels in off-grid areas. Further incubation of technology, business and education models is also being pursued in collaboration with sustainable development NGOs committed to enabling the 1.4 billion at the economic Base of the Pyramid (BOP).

FASTBUS Demonstration Systems

This paper will provide a demonstration of basic FASTBUS hardware and test software. The systems will include single crate segments, simple computer I/O, a fast sequencer and memory, some simple diagnostic and display devices and a UNIBUS to FASTBUS processor interface. The equipment will be set up to show the basic FASTBUS protocols and timing transactions, as well as some of the general initialization software features.

Status and Future of FASTBUS

This paper primarily focuses on developments which are needed to make FASTBUS a viable option for future experiments and control systems. The basic tools available or under development are discussed.

Applicability of the FASTBUS Standard to Distributed Control

The new FASTBUS standard has been designed to provide a framework for distributed processing in both experimental data acquisition and accelerator control. The features of FASTBUS which support distributed control are a priority arbitration scheme which allows intercrate as well as intracrate message flow between processors and slave devices; and a high bandwidth to permit efficient sharing of the data paths by high-speed devices. Sophisticated diagnostic aids permit system-wide error checking and/or correction. Software has been developed for large distributed systems. This consists of a system data base description, and initialization algorithms to allocate address space and establish preferred message routes. A diagnostics package is also being developed, based on an independent Ethernet-like serial link. The paper describes available hardware and software, on-going developments, and current applications.