David B. Gustavson
Stanford University
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Featured researches published by David B. Gustavson.
annual european computer conference | 1989
Knut Alnaes; Emst H. Kristiansen; David B. Gustavson; David V. James
The Scalable Coherent Interface Project (IEEE P1596) is establishing an interface standard for very-high-performance multiprocessors, supporting a cache-coherent-memory model scalable to systems with up to 64K nodes. The P1596 Scalable Coherent Interface (SCI) will supply a peak bandwidth per node of 1 Gb/s. The SCI standard should facilitate assembly of processor, memory, I/O and bus bridge cards from multiple vendors into massively parallel systems with throughput far above what is possible today. The SCI standard encompasses two levels of interface, a physical level and a logical level. The physical level specifies electrical, mechanical and thermal characteristics of connectors and cards that meet the standard. The logical-level describes the address space, data transfer protocols, cache coherence mechanisms, synchronization primitives and error recovery. Logical-level issues such as packet formats, packet transmission, transaction handshake, flow control, and cache coherence are addressed.<<ETX>>
international symposium on microarchitecture | 1984
David B. Gustavson
The major issues of bus design are illuminated in this easy-to-understand introduction to computer buses¿the communication paths that are revolutionizing interactions between microprocessor systems.
international symposium on microarchitecture | 1983
David B. Gustavson; John G. Theus
In modern high-speed systems, avoid wire-OR logic in transmission lines whenever possible or make allowances for its foibles.
Archive | 1992
Stein Gjessing; David B. Gustavson; James R. Goodman; David V. James; Ernst Kristiansen
This article discusses the current status of the Scalable Coherent Interface (SCI), IEEE standards project P1596. The SCI cache coherence protocol is scalable (up to 64K processors can be supported), efficient (memory is not involved in the common pairwise-sharing updates), and robust (data can be reliably recovered by software after transmission errors). Scalability is achieved by having the memory directory identify only the first processor sharing a cache line; other processors sharing the same line are identified by entries in a distributed doubly linked list.
IEEE Transactions on Nuclear Science | 1978
R.L. Anderson; W. W. Ash; David B. Gustavson; Keith M. Rich; D. Ritson; J. R. Johnson; R. Prepost; D. E. Wiser
We present results from test beam measurements at SLAC with prototype modules for the MAC detector at PEP. The modules consist of planes of proportional wires interleaved with lead sheets (shower counter) or iron plates (hadron calorimeter).
IEEE Transactions on Nuclear Science | 1989
David B. Gustavson
IEEE P1596, the scalable coherent interface (SCI), formerly known as SuperBus is based on experience gained during the development of FASTBUS (IEEE 960), Futurebus (IEEE 896.1) and other modern 32-bit buses. SCI goals include a minimum bandwidth of 1 Gb/s per processor; efficient support of a coherent distributed-cache image of shared memory; and support for segmentation, bus repeaters, and general switched interconnections like Banyan, Omega, or full crossbar networks. To achieve these goals, SCI must sacrifice the immediate handshake characteristics of the present generation of buses in favour of a packetlike split-cycle protocol. Wire-ORs, broadcasts, and even ordinary passive bus structures must be avoided. However, a lower performance (1 Gb/s per backplane instead of per processor) implementation using a register insertion ring architecture on a passive backplane appears to be possible using the same interface as for the more costly switch networks. The author summarizes current directions and reports the status of the work in progress. >
Microprocessors and Microsystems | 1986
David B. Gustavson
Abstract Fastbus is a modular data bus system for data acquisition and data processing. It is a multiprocessor system with multiple bus segments which operate independently but link together for passing data. It operates asynchronously to accommodate very high and very low speed devices over long or short paths, using handshake protocols for reliability. It can also operate synchronously with pipelined handshakes for transfer of data blocks at maximum speed. The paper summarizes the goals, history and motivation for the Fastbus. The structure of the Fastbus system is described in general and some details of its operation are introduced.
IEEE Transactions on Nuclear Science | 1983
Helmut V. Walz; David B. Gustavson
A SNOOP Diagnostic Module for FASTBUS is under development at SLAC. The SNOOP Module resides on a FASTBUS crate segment and provides diagnostic monitoring and testing capability. It consists of a high-speed ECL front-end to monitor and single-step segment operations, a simple master interface, and a control processor with two serial communication ports. Module features and specifications are summarized, and prototype hardware is shown.
ieee computer society international conference | 1992
David B. Gustavson; Ernst Kristiansen
The uses of the Scalable Coherent Interface (SCI) are examined. SCI was developed to support closely coupled multiprocessors and their caches in a distributed shared-memory environment, but its scalability and the efficient generality of its architecture make it work very well over a wide range of applications. It can replace a local area network for connecting workstations on a campus. It can be a powerful I/O channel for a supercomputer. It can be the processor-cache-memory-I/O connection in a highly parallel computer. It can gather data from enormous particle detectors and distribute them among thousands of processors. It can connect a desktop microprocessor to memory chips a few millimeters away, disk drives a few meters away, and servers a few kilometers away.<<ETX>>
IEEE Transactions on Nuclear Science | 1986
David B. Gustavson; Helmut V. Walz
The development of a diagnostic module for FASTBUS has been completed. The Snoop Module is designed to reside on a Crate Segment and provide high-speed diagnostic monitoring and testing capabilities. Final hardware details and testing of production prototype modules are reported. Features of software under development for a stand-alone single Snoop diagnostic system and Multi-Snoop networks will be discussed.