L. Paffrath

The SLAC Scanner Processor: A FASTBUS Module for Data Collection and Processing

A new, general purpose, programmable FASTBUS module, the SLAC Scanner Processor (SSP), is introduced. Both hardware and software elements of SSP operation are discussed. The role of the SSP within the upgraded Mark II Detector at SLAC is described.

The Digital Correction Unit: A Data Correction/Compaction Chip

The Digital Correction Unit (DCU) is a semi-custom CMOS integrated circuit which corrects and compacts data for the SLD experiment. It performs a piece-wise linear correction to data, and implements two separate compaction algorithms. This paper describes the basic functionality of the DCU and its correction and compaction algorithms.

A New Timing System for the Stanford Linear Collider

In order to be able to meet the goals of the Stanford Linear Collider, a much more precise timing system had to be implemented. This paper describes the specification and design of this system, and the results obtained from its use on 1/3 of the SLAC linac. The functions of various elements are described, and a programmable delay unit (PDU) is described in detail.

The front-end analog and digital signal processing electronics for the drift chambers of the Stanford Large Detector

The front-end signal processing electronics for the drift chambers of the Stanford Large Detector (SLD) at the Stanford Linear Collider are described. The system is implemented with printed-circuit boards which are shaped for direct mounting on the detector. Typically, a motherboard comprises 64 channels of transimpedance amplification and analog waveform sampling, analog-to-digital conversion, and associated control and readout circuitry. The loaded motherboard thus forms a processor which records low-level waveforms from 64 detector channels and transforms the information into a 64 kB serial data stream. The package performs calibration functions, measures leakage currents on the wires, and generates wire hit patterns for triggering purposes. The construction and operation of the electronic circuits utilizing monolithic, hybridized, and programmable components are discussed. >

An I/O Register to FASTBUS Interface

An input/output register to FASTBUS interface (IORFI) has been designed which provides an inexpensive and simple means to connect a computer to a FASTBUS backplane segment. The FASTBUS backplane interface is built on a single width FASTBUS module. It is connected to a computer by two 16-bit parallel input registers and two 16-bit parallel output registers, which makes the interface computer-non-specific. This paper describes the operational characteristics of this interface, its advantages, limitations, and briefly, the uses to which it has been put.

dE/dx Electronics for Mark II Experiment at SLAC

This paper describes a 100 MHz pulse digitizer for dE/dx measurements on the MARK II drift chamber at SLAC. The electronics provides the read-out of the detectors 5832 sense wires, organized in 336 wires/FASTBUS crate. The system is based on a 16-channel FASTBUS module. The basic element of the module is the TRW 6-bit Flash-ADC.

FASTBUS Demonstration Systems

This paper will provide a demonstration of basic FASTBUS hardware and test software. The systems will include single crate segments, simple computer I/O, a fast sequencer and memory, some simple diagnostic and display devices and a UNIBUS to FASTBUS processor interface. The equipment will be set up to show the basic FASTBUS protocols and timing transactions, as well as some of the general initialization software features.

A FASTBUS Interface for the 3081/E

The design of a FASTBUS interface to the 3081/E is presented. The interface consists of two boards, one specific to FASTBUS, the other usable by other interfaces to the 3081/E. The FASTBUS board is a dual-ported slave, permitting access from either of two cable segments. The general purpose board supports transfers to and from 3081/E memory and provides control of program execution. It also has several features which facilitate software debugging.

Applicability of the FASTBUS Standard to Distributed Control

The new FASTBUS standard has been designed to provide a framework for distributed processing in both experimental data acquisition and accelerator control. The features of FASTBUS which support distributed control are a priority arbitration scheme which allows intercrate as well as intracrate message flow between processors and slave devices; and a high bandwidth to permit efficient sharing of the data paths by high-speed devices. Sophisticated diagnostic aids permit system-wide error checking and/or correction. Software has been developed for large distributed systems. This consists of a system data base description, and initialization algorithms to allocate address space and establish preferred message routes. A diagnostics package is also being developed, based on an independent Ethernet-like serial link. The paper describes available hardware and software, on-going developments, and current applications.

Physical packaging and organization of the drift chamber electronics system for the Stanford Large Detector

The logical organization, physical packaging, and operation of the drift chamber electronics for the Stanford Large Detector are described. The system processes signals from approximately 7000 drift wires and is unusual in that most electronic functions are packaged on printed circuit boards within the detector. The circuits reside on signal-processing motherboards, controller boards, signal-transition boards, power-distribution boards, and fiber-optics-to-electrical conversion boards. The interaction and interconnection of these boards with respect to signal and control flow are presented. >