R. Tielert

Benefits of vertically stacked integrated circuits for sequential logic

Future demands for performance of electronic systems will push the development of three-dimensional (3-D) packaging technologies. Up to now 3-D stacking techniques are just used to realize high density memory modules. In this paper we investigate problems and solutions of sequential logic circuit design for vertically stacked integrated circuits (VIC). We analyze a test strategy and a 3-D placement tool for VICs that allows us to generate globally optimized circuit layouts by a 3-D arrangement of gates. Our focus is on test overhead obtained by the proposed test strategy for VICs and the reduction of wiring space attained by 3-D routing. Additionally we discuss the effect of our 3-D placement procedure on fault coverage. The results obtained using this procedure in different circuit layouts for 3-D circuits are compared to single chip solutions.

A pure CMOS surface micromachined integrated accelerometer

A pure CMOS integrated accelerometer was realised using surface micromachining as structural technique. The samples were fabricated by a 14 mask 0.8 /spl mu/m CMOS standard process in a Siemens production line. Only the standard layers of the process (350 nm polysilicon and 600 nm oxide as sacrificial layer) are used to build up the surface micromachined device. Sensor release and antisticking are also CMOS-compatible. The movement of a seismic mass normal to the chip surface is capacitively detected (open loop) and transformed on chip into a digital output signal by a robust circuit for measuring sub-fF capacitance differences. Parasitics are suppressed on chip. The sensor was designed to measure accelerations up to 50 g. A resolution of /spl plusmn/0.6 g corresponding to a capacitance change of /spl plusmn/0.1 fF was observed.

A pure CMOS surface-micromachined integrated accelerometer

Abstract A pure CMOS integrated accelerometer has been realized using surface micromachining as the structural technique. The samples are fabricated by a 14-mask 0.8 μm CMOS standard process in a Siemens production line. Only the standard layers of the process (350 nm polysilicon and 600 nm oxide as sacrificial layer) are used to build up the surface-micromachined device. Sensor release and antisticking are also CMOS-compatible. The movement of a seismic mass normal to the chip surface is capacitively detected (open loop) and transformed on chip into a digital output signal by a robust circuit for measuring sub-femtofarad capacitance difference. Parasitics are suppressed on chip. The sensor is designed to measure accelerations up to 50g. A resolution of ± 0.6g, corresponding to a capacitance change of ± 0.1fF, is observed.

Low power UWB pulse radio transceiver front-end

In this paper, we propose a low power architecture to extract UWB pulse radio signals from noise level in the presence of narrow band interfering channels. The receiver consists of many narrow band-pass filters, which extract energy either from transmitted UWB signal, interfering channels or noise. Transmitted UWB data can be extracted by statistical correlation of multiple band-pass filter outputs. Super-regenerative receivers, tuned within UWB spectrum, act as band-pass filters. Summer and comparator perform statistical correlation. The test structure of transceiver has been implemented on 0.18 mum CMOS technology, active area of 3.15 mm2, and data exchange rate of 8 Mbits/s with power consumption of 2.6 mw at 1.5 V

Super-regenerative UWB impulse detector with synchronized quenching mechanism

This paper presents low power fully integrated super-regenerative UWB impulse detector with automatic adjustment of incoming pulses at highly sensitive region by using synchronized voltage controlled quenching mechanism. In-band and out-of-band interferences are eliminated by logic comparison and redundancy check between the outputs of multiple super-regenerators tuned within UWB spectrum. The test structure has been implemented on 0.18 mum CMOS technology, active area of 1.4 mm2. The UWB signal to in-band interferer ratio of -36 dB is achieved with sensitivity of -95 dBm at data rate of 20 Mb/s and power consumption of 5 mW at 1.5 V.

A new fitting approach for online electrocardiogram component waves delineation

A real-time capable and accurate template-based fitting approach for the detection and delineation of all the QRS-complexes, P-, and T-waves is presented. The ECG features extraction is accomplished with a very low amount of ECG signal preprocessing. The performance of our proposed algorithm is validated using ECG records from both the MIT-BIH Arrhythmia and QT standard databases. All of the ECG component waves detectors achieved very high detection rates, detecting correctly up to 3015, 3013, and 3010 QRS-complexes, P- and T-waves respectively from 3015 cardiac beats. The delineation results showed that the standard deviations of the errors are within the tolerance limits.

A 0.11mm/sup 2/ low-power A/D-converter cell for 10b 10MS/s operation

A 10 bit 10 MS/s cyclic analog-to-digital converter has been implemented using 0.18 /spl mu/m CMOS technology. The converter was optimized with respect to area and power consumption in order to allow the integration of a multichannel array within a complex logic chip. The power consumption is 9.5 mW. The area per A/D-converter cell is 0.11 mm/sup 2/. The proposed cyclic converter architecture together with some implementation aspects, like working with one amplifier only and reusing the signal capacitors for the common-mode feedback helped to meet the requirements of the application.

Low power complementary-colpitts self-quenched super-regenerative ultra-wideband (UWB) bandpass filter in CMOS technology

This paper presents the complementary colpitts self-quenched super-regenerative ultra-wideband (UWB) bandpass filter for low power, low cost and medium data rate wireless communication systems. The high gain, large bandwidth and low power consumption are the attractive properties of self-quenched super-regenerative filters for UWB systems. The bandwidth of 1.5GHz across the central frequency of 7.5GHz is measured for complementary colpitts self-quenched super-regenerative filter. The test structure has been implemented on 0.18μm CMOS technology. The data rate of 10Mb/s is achieved for detecting −95dBm signals with power consumption of 1mW at 1.5V.

Fully integrated self-quenched super-regenerative UWB impulse detector

This paper presents the fully integrated self-quenched super-regenerative UWB impulse detector for low power and medium data rate wireless applications. The high gain, large bandwidth and low power consumption are the attractive properties of self-quenched super regenerative receivers for UWB system. The bandwidth of 1.5GHz across the central frequency of 7GHz is measured for self-quenched super-regenerative receiver. The test structure has been implemented on 0.18mum CMOS technology. The data rate of 4MHz is achieved for detecting -95dBm signals with power consumption of 1mW at 1.5V.

3.1-to-7GHz UWB impulse radio transceiver front-end based on statistical correlation technique

This paper presents the UWB impulse radio transceiver front-end based on statistical correlation technique between multiple band-pass filters tuned within UWB spectrum. The band-pass filters can detect energy either from transmitted UWB impulses, interfering channels or noise. Transmitted UWB impulses can be extracted by statistical correlation in between the outputs of band-pass filters. Super-regenerative receivers, tuned within 3.1-to-7 GHz UWB spectrum, act as band-pass filters. Summer and comparator perform statistical correlation. The test structure of transceiver has been implemented on 0.18 mum CMOS technology, active area of 1.44 mm2, sensitivity of -99 dBm and -30 dB SIR with power consumption of 15 mW at 1.5 V.