R. Travaglini

Construction and test of the final CMS Barrel Drift Tube Muon Chamber prototype

A prototype of the CMS Barrel Muon Detector incorporating all the features of the final chambers was built using the mass production assembly procedures and tools. The performance of this prototype was studied in a muon test beam at CERN and the results obtained are presented in this paper.

A PowerPC-based control system for the Read-Out-Driver module of the ATLAS IBL

The ATLAS experiment at LHC planned to upgrade the existing Pixel Detector with the insertion of an innermost silicon layer, called Insertable B-layer (IBL). A new front-end ASIC has been foreseen (named FE-I4) and it will be read out with improved off-detector electronics. In particular, the new Read-Out Driver card (ROD) is a VME-based board designed to process a four-fold data throughput. Moreover, the ROD hosts the electronics devoted to control operations whose main tasks are providing setup busses to access configuration registers on several FPGAs, receiving configuration data from external PCs, managing triggers and running calibration procedures. In parallel with a backward-compatible solution with a Digital Signal Processor (DSP), a new ROD control circuitry with a PowerPC embedded into an FPGA has been implemented. In this paper the status of the PowerPC-based control system will be outlined with major focus on firmware and software development strategies.

Offline calibration procedure of the CMS Drift Tube detectors

The barrel region of the Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider is instrumented with Drift Tube (DT) detectors. This paper describes in full details the calibration of the DT hit reconstruction algorithm. After inter-channel synchronization has been verified through the appropriate hardware procedure, the time pedestals are extracted directly from the distribution of the recorded times. Further corrections for time-of-flight and time of signal propagation are applied as soon as the three-dimensional hit position within the DT chamber is known. The different effects of the time pedestal miscalibration on the two main hit reconstruction algorithms are shown. The drift velocity calibration algorithm is based on the meantimer technique. Different meantimer relations for different track angles and patterns of hit cells are used. This algorithm can also be used to determine the uncertainty on the reconstructed hit position.

Implementation and tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card

The Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a Readout-Driver card (ROD) for data processing. The ROD hosts the electronics devoted to control operations implemented both with a back-compatible solution (using a Digital Signal Processor) and with a PowerPC embedded into an FPGA. In this document major firmware and software achievements concerning the PowerPC implementation, tested on ROD prototypes, will be reported.

ATLAS IBL: integration of new HW/SW readout features for the additional layer of Pixel Detector

An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design. The front-end electronics features a new readout ASIC, named FE-I4, which requires new off-detector electronics, currently realized with two VME-based boards: the Back Of Crate module (BOC) implements optical I/O functionality and the ReadOut Driver module (ROD) implements data processing functionality, plus a Timing Interface Module (TIM). This paper presents a proposal for the IBL readout system, mainly focusing on the ROD board.

Design and Test of the Off-Detector Electronics for the CMS Barrel Muon Trigger

Drift Tubes chambers are used in the CMS barrel for tagging the passage of high Pt muons generated in a LHC event and for triggering the CMS data read out. The Sector Collector (SC) system synchronizes the track segments built by trigger modules on the chambers and deliver them to reconstruction processors (Track Finder, TF) that assemble full muon tracks. Then, the Muon Sorter (MS) has to select the best four candidates in the barrel and to filter fake muons generated by the TF system redundancy. The hardware implementations of the Sector Collector and Muon Sorter systems satisfy radiation, I/O and fast timing constraints using several FPGA technologies. The hardware was tested with custom facilities, integrated with other trigger subsystems, and operated in a beam test. A test beam on a 40 MHz bunched beam validated the local trigger electronics and off-detector prototype cards and the synchronization tools. The CMS Magnet Test and Cosmic challenge in 2006 proved stable and reliable operation of the Drift Tubes trigger and its integration with other trigger systems and with the readout system. Constraints, design, test and operation of the modules are presented.

A Multi-Channel PCI Express Readout Board Proposal for the Pixel Upgrade at LHC

After having designed and commissioned the readout electronics currently implemented in the Insertable B-Layer, Layer 1 and Layer 2 of the ATLAS Pixel Detector (B-Layer and Disk readout electronics is under commissioning), we have designed a new readout electronic board looking primarily at the upgrade of the LHC Pixel Detectors. Two prototypes of a PCI Express board, namely Pixel_ROD, featuring all the minimal input-outputs interfaces to address the future front-end readout electronics, have already been fabricated and tested. The digital protocols used for the GBTx and for the RD53A chips have been investigated and we have been able to emulate physically a data acquisition chain interfacing with these components. The Pixel_ROD board might fit a variety of applications, from a test stand to qualify the RD53a chips that are currently under fabrication to a front-end physical emulator, designed via firmware, adaptable to any detector. As we have been working for years on the hardware and firmware of the IBL ReadOut Driver (ROD) card, we can also use this prototype board as a multi-channel FE-I4 emulator. An entire module of a Pixel Detector can be emulated by generating a very fast flux of data according to the desired protocol: FE-I4 compatible format for the current detector of ATLAS experiment and Aurora 64b/66b protocol for the next RD53A chip that will be used for ATLAS and CMS Pixel Detectors. The Pixel_ROD board in fact, features internal high-speed transceivers to interface easily from and to any other electronic board, electrically and/or optically, at the current desired bandwidth of the experiments for LHC. We have already started to carry out some tests, with the supervision of the ATLAS TDAQ collaboration, to interface with the FELIX card, either for data-acquisition or trigger functions, in view of any application towards the LHC phase-2 upgrade.

Firmware development and testing of the ATLAS IBL Read-Out Driver card

The ATLAS Experiment is reworking and upgrading systems during the current LHC shutdown. In particular, the Pixel detector is inserting an additional inner layer called Insertable B-Layer (IBL). The Read-Out Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL’s off-detector DAQ system. The strategy for IBL ROD firmware development focused on migrating and tailoring HDL code blocks from Pixel ROD to ensure modular compatibility in future ROD upgrades, in which a unified code version will interface with IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBL DAQ testbench using a realistic frontend chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBL ROD data path implementation, tested in testbench and on ROD prototypes, will be reported. Recent Pixel collaboration efforts focus on finalizing the hardware and firmware tests for IBL. The time plan is to approach a final IBL DAQ phase by the end of 2014.