R. V. K. Pillai

A low power approach to floating point adder design

We present a new architecture of a low power floating point adder, that is fast and has low latency. The functional partitioning of the adder into three distinct, controlled data paths allows activity reduction. During any given operation cycle, only one of the data paths is active, during which time, the logic assertion status of the circuit nodes of the other data paths are held at their previous states. Critical path delay and latency are reduced by incorporating speculative rounding and pseudo leading zero anticipation logic as well as data path simplifications. The proposed scheme offers a 10/spl times/ reduction in power consumption in comparison to that of conventional high speed floating point adders that use leading zero anticipation logic, for IEEE single precision floating point data format. The reduction in power delay product is about 16/spl times/. The corresponding figures for double precision units are around 40/spl times/ and 66/spl times/ respectively.

A Low Power Approach to Floating Point Adder Design for DSP Applications

The demand for high performance, low power floating point adder cores has been on the rise during the recent years particularly for DSP applications. In this paper, we present a new architecture for a low power, IEEE compatible, floating point adder, that is fast and has low latency. The functional partitioning of the adder into three distinct, clock gated data paths allows activity reduction. The switching activity function of the proposed adder is represented as a three state FSM. During any given operation cycle, only one of the data paths is active, during which time, the logic assertion status of the circuit nodes of the other data paths are held at their previous states. Critical path delay and latency are reduced by incorporating speculative rounding and pseudo leading zero anticipatory logic as well as data path simplifications. In contrast to conventional high speed floating point adders that use leading zero anticipatory logic, the proposed scheme offers a worst case power reduction of 50%.

Power implications of additions in floating point DSP-an architectural perspective

This work targets experimental characterization of the architectural power implications of floating point adders that form part of DSP cores. High level models that characterize the power behavior of floating point adders are developed. Instrumented digital filter programs that emulate a DSP multiply-accumulate unit form the core of our experimental platform. The experiments substantiate the validity of our transition activity scaling based approach for the design of low power floating point adders. The worst case power reduction offered by the proposed transition activity scaled triple data path floating point adder (TDPFADD) is consistently above 50%. The corresponding reduction in power delay product is better than 70%.

Evaluation of 1's complement arithmetic for the implementation low power CMOS floating point adders

In CMOS logic implementations, the architecture of functional units reflects the algorithmic cause effect relations as far as logic functionality, structural complexity, power consumption and speed of operation are concerned. The paper addresses the architectural evaluation of arithmetic units based on 1s complement algorithms for the implementation of low power floating point units. Our investigations suggest the suitability of 1s complement adders for the realization of low power floating point adders/subtracters, accumulators and multiply accumulators. The power consumption and silicon area of 1s complement adders that realize functions of the type |A-B| involving integer data A and B, are around 50% of that of their 2s complement counterparts.

Power implications of precision limited arithmetic in floating point FIR filters

This work targets characterization of the architectural power implications of precision limited arithmetic operations during floating point FIR filtering. Instrumented digital filter programs that emulate a DSP multiply-accumulate unit form the core of our experimental platform. The experiments substantiate the validity of our transition activity scaling based approach for the design of low power floating point adders and multiply accumulators (MACs). With precision limited low pass filtering, the worst case power reduction offered by the proposed transition activity scaled triple data path floating point adder (TDPFADD) is better than 60%. The corresponding reduction in power delay product is better than 75%.

An IEEE Compliant Floating Point MAF

In this paper1. we present a new architecture for low power floating point multiply — accumulate (MAC) fusion. The proposed architecture supports IEEE and non IEEE rounding modes. The functional partitioning of the adder segment of the MAC into three distinct, clock gated data paths allows activity reduction. The switching activity function of the adder is represented as a three state FSM. During any given operation cycle, only one of the data paths is active, during which occasion, the logic assertion status of the circuit nodes of the other data paths are maintained at their previous states. Critical path delay and latency are reduced by incorporating speculative rounding and data path simplifications. The proposed scheme offers a worst case power reduction of around 25%, in contrast to a comparable scheme reported in literature.

On the power implications of floating point addition in IIR filters

In floating point DSP applications, filtering of data samples is one of the most demanding operations. While the specification driven filter design delivers transfer functions satisfying target applications, certain implementations of these transfer functions can result in filters exhibiting various undesirable artifacts. This work addresses the characterization of the relative power implications of floating point Direct form II and Transposed Direct form II IIR filters. In programmable DSP applications, (compared to Transposed Direct form II realizations), Direct form II realizations offers better power reduction as far as the power implications of the floating point adder segment of DSPs are concerned. During filtering of white noise samples, the alignment driven data path switchings of transposed realizations had been found to be around 3 to 4 times that of direct form realizations. Performance of the same experiment involving audio samples substantiates the above findings.

Arithmetically sub-optimal floating point digital filters an architectural power perspective

In CMOS floating point hardware design, transition activity scaling of functional units, taking into account the limitations of machine arithmetic, offers promising results as far as architectural power optimization of these units is concerned. This work targets characterization of the architectural power implications of floating point adder cores of DSP data paths during implementation of arithmetically sub-optimal floating point digital filters. Instrumented digital filter programs that emulate a DSP multiply-accumulate unit form the core of our experimental platform. With a class of arithmetically sub-optimal band pass/stop filters having a normalized centre frequency of 0.5, the transition activity scaled triple data path floating point adder scheme offers a power reduction of better than 75%.

A low power floating point accumulator

In CMOS logic implementations, the architectural/algorithmic power/delay/area implications of functional units are crucial as far as design economies of the target application are concerned. This paper addresses the architectural design of a low power floating point accumulator by using a transition activity scaled triple data path floating point adder core. The proposed scheme offers a worst case power reduction of 50% in comparison to schemes that use conventional floating point adders. The reduction in power delay product is better than 3X.