R. van Dalen

Manufacturing of high aspect-ratio p-n junctions using vapor phase doping for application in multi-Resurf devices

A new technique to manufacture vertical Resurf devices is presented, in which the alternating p-n junctions in the drift region are formed by a combination of trench etching and vapor phase doping (VPD). Scanning capacitance microscopy (SCM) was performed to investigate these deep p-n junctions, showing a uniform doping profile along the full depth of the devices. Electrical measurements on such Resurf diodes display an increase in breakdown voltage from 30 V to 145 V for a device with a 10 /spl mu/m deep drift region doped at 3.5/spl times/10/sup 16/ cm/sup -3/. Such a concept leads to prediction of a specific on-resistance well below the silicon limit for an equivalent MOSFET.

Industrialisation of Resurf Stepped Oxide Technology for Power Transistors

The interaction of fabrication processes and device performance in RSO (resurf stepped oxide) transistors is explored in this paper. Critical process steps for achieving good control of resurf behaviour are the etching of the deep trenches, their refill with thick oxide and etch-back to define the oxide step. Optimum conditions result in typical Rspec of 46mOmega.mm2 at a BVdss of 80V and defect densities less than 3 cm-2. Qgd values of about 9 nC/mm2 limit the single-gate polysilicon RSO structure to low frequency applications, such as switching automotive loads. Simulation has indicated that the introduction of a split-polysilicon RSO structure, with source-connected bottom poly, gives excellent Rds.Qgd values, which are an order of magnitude lower, hence extending the scope of the technology to high frequency applications

Vertical multi-RESURF MOSFETs exhibiting record low specific resistance

For the first time, experimental results are presented of vertical RESURF MOSFETs in which the alternating pn-junctions in the drift region are formed by a combination of a trench etch and vapor phase doping (VPD) process. Such a process allows very small pitch sizes, offering unprecedentedly low specific resistance. A reverse breakdown voltage of 165 V is obtained for devices with a 10 /spl mu/m drift region doped at 5/spl times/10/sup 15/ cm/sup -3/, with a corresponding specific resistance of 208 m/spl Omega//spl middot/mm/sup 2/ (V/sub g/=10 V). These are the first MOSFETs to break the 1D silicon limit below 200 V, with a specific resistance 30% below current state-of-the-art devices.

Hot carrier degradation of HV-SOI devices under off-and on-state current conditions

Optimisation of High Voltage (HV) devices is typically governed by life-time considerations, most notably requirements for sufficient immunity against Hot Carrier Injection (HCI). Based on insight in the different degradation mechanisms in HV-SOI, we have identified distinctive acceleration methodologies for on- and off-state stress conditions.

A scalable trench etch based process for high voltage vertical RESURF MOSFETs

In this work, for the first time, vertical RESURF MOSFETs manufactured using a trench etch and vapor phase doping process depict a breakdown voltage above 300V. We prove that this concept is scalable to a much higher breakdown voltage range. The device features a record low specific resistance of 0.98/spl Omega/mm/sup 2/ with a breakdown voltage of 473V. This best result to-date for any superjunction technology proves to be a good alternative to the multi-epitaxy technique commercially in use.

Breaking the silicon limit using semi-insulating Resurf layers

In this paper, we present results on a novel multi-Resurf technique that involves the use of semi-insulating layers, in which the flattening of the electric field profile is achieved by virtue of a small leakage current. Unlike conventional Resurf devices, this technique provides a perfect flattening of the field profile without the requirement of an accurate charge balance. Experimental results show an increase in steady-state breakdown voltage from 19 to 85 V for a device having 4 /spl mu/m drift regions doped at 5e16 cm/sup -3/, with corresponding R/sub on/ below the silicon limit.

Vertical RESURF diodes manufactured by deep-trench etch and vapor-phase doping

A new technique to manufacture vertical reduced surface field (RESURF)/superjunction devices is presented, in which the alternating p-n-junctions in the drift region are formed by a combination of a trench etch and vapor-phase doping process. Electrical measurements on Schottky RESURF diodes exhibit breakdown voltages up to 160 V with an on-resistance of 182 m/spl Omega/.mm/sup 2/ using a 10 /spl mu/m n-type drift region doped at 7.5/spl middot/10/sup 15/ cm/sup -3/. We show experimentally that such a device concept is able to display specific on-resistance well below the one-dimensional silicon limit and is a good candidate to manufacture vertical power RESURF MOSFETs.

Using thin emitters to control BVce0 effects in punch-through diodes for ESD protection

We present results of a novel punch-through diode structure which uses a thin SiGe emitter to effectively suppress impact-ionization related (BVce0) effects that typically start to dominate the electrical characteristics of conventional punch-through devices at voltages above 2.5..3.0 V, resulting in the occurrence of negative resistances (snap-back) and severely limiting the application range.

Development of high-side capable thyristors in thin SOI technology

In this paper we describe the development of integrated lateral thyristors in NXPs proprietary HV-SOI technology [1]. Thyristors are typically used for their extreme high-current capability or their zero-crossing switch-off, that allow easy implementation of phase-controlled power conversion. In this work, the main motivation to select thyristors is their ability to operate as an efficient switch under high-side (HS) conditions. The latter differs considerably from conventional thyristor operation, resulting in dedicated device optimisation. Also, the breakdown voltages (>650V) far exceed any previous work on thin SOI [2]. We present a detailed analysis of the thyristor operation and highlight the typical problems associated with the implementation on SOI.