R. Williams

Noise in Silicon Nanowires

The current-voltage and noise characteristics of bridging silicon wires have been measured at room temperature. From the linear current-voltage characteristics the bulk and contact resistance contributions are extracted and modeled. The excess noise observed at low frequencies is interpreted in terms of bulk and contact noise contributions, with the former comparable, in terms of Hooge parameter values, to the low noise levels observed in high-quality silicon devices. The contact noise is significant in some devices and is attributed to the impinging end of the bridging nanowires

History Erase Effect in a Non-Volatile Memristor

This work presents a detailed study of the nonlinear dynamics of a tantalum oxide memristor recently fabricated at Hewlett Packard Labs. Our investigations uncover direct current, quasi-static, and alternating current behavior of the nanodevice. A thorough study of the dynamics emerging in the nanoscale element under various input/initial condition combinations reveals a fundamental property of the tantalum oxide device, which was unnoticed so far. The initial condition has no effect on the steady-state operation of the memristor under non-zero input. This property, known as fading memory in system theory, implies the uniqueness of asymptotic behavior of the memristor. The progressive input-induced memory erase phenomenon is solely determined by the switching dynamics of the nanodevice, mathematically described by the state evolution function, which governs the rate of evolution of the memristor state. A constant-sign DC input will activate on or off switching dynamics only. Consequently, due to the limited on/off memductance ratio, the memristor will asymptotically attain a fully-conducting or highly-resistive state, irrespective of the initial condition. Most interestingly, under AC periodic excitations, it is the pronounced asymmetry in the state dependence of on and off switching processes which is at the basis of the reported history erase effect. It is important to point out that this novel fading memory phenomenon does not compromise the nonvolatile behavior of the nanostructure. In fact, despite the device may be stimulated so as to forget its past history, it still has a continuum of analog nonvolatile memory states.

Effect of Conductance Variability on Resistor-Logic Demultiplexers for Nanoelectronics

On a mixed-scale nanoelectronic crossbar, in which nanowires cross CMOS-scale wires at right angles, a demultiplexer circuit may be laid out using configurable resistors at the crosspoint junctions. This circuit can function as an interface between conventional CMOS microelectronic circuitry and the smaller nanocircuitry by allowing a few CMOS address lines to control a much larger number of nanowires. The voltage margin properties of these resistor-demultiplexers can be improved by basing them on error-correcting codes. In any real fabrication process, the conductances of the resistors in the demultiplexer circuit will be distributed over a range of values. Using simulation, we investigate how variability in the conductances affects the voltages on the output lines of the demultiplexer, and the related voltage margin of the overall circuit. The simulation results provide a simple quantitative relationship revealing that the voltage variability is smaller than the component variability

Defect Tolerance Based on Coding and Series Replication in Transistor-Logic Demultiplexer Circuits

We present a family of defect tolerant transistor-logic demultiplexer circuits that can defend against both stuck-ON (short defect) and stuck-OFF (open defect) transistors. Short defects are handled by having two or more transistors in series in the circuit, controlled by the same signal. Open defects are handled by having two or more parallel branches in the circuit, controlled by the same signals, or more efficiently, by using a transistor-replication method based on coding theory. These circuits are evaluated, in comparison with an unprotected demultiplexer circuit, by: 1) modeling each circuits ability to tolerate defects and 2) calculating the cost of the defect tolerance as each circuits redundancy factor R, which is the relative number of transistors required by the circuit. The defect-tolerance model takes the form of a function giving the failure probability of the entire demultiplexer circuit as a function of the defect probabilities of its component transistors, for both defect types. With the advent of defect tolerance as a new design goal for the circuit designer, this new form of performance analysis has become necessary.

Surface engineering for resolution enhancement in nanoimprint lithography

Nanoimprinting lithography was initiated as an alternative way to achieve nanoscale structures with high throughput and low cost. We have developed a UV-nanoimprint process to fabricate 34x34 crossbar circuits with a half-pitch of 50 nm (equivalent to a bit density of 10 Gbit/cm2). Our resist was of a single layer, which required fewer processing steps than any bi-layer process, but yielded high quality results. By engineering the surface energy of the substrate, we also eliminated the problem of trapped air during contact with the mold due to non-conformal contact such that it spreads the resist and expels trapped air. Resist adhesion to the gaps between features in the mold during mold separation is a challenge that becomes more severe as the pitch size shrinks. We have improved the resist adhesion to the substrate by applying a monolayer of surface linker molecule on the substrate surface. The surface linker bonded the resist to the substrate surface chemically and produced fine imprinted patterns at 30 nm hp.

Memory Loss in a Tantalum Oxide Memristor

The tantalum oxide memristor may have a promising future as key element in innovativevery-high speed ultra-low power extra-large density nonvolatile memories. It is therefore timely andrelevant to investigate the nonlinear dynamics of this device in view of the interesting opportunities itmay open up in the world of electronics in the years to come. In numerical simulations of an accuratemodel of the tantalum oxide memristor manufactured at Hewlett Packard Labs we observed a surprisingphenomenon which was never reported earlier. Under AC periodic excitation the memristorexhibits unique asymptotic behaviour, irrespective of the initial condition. Thus the device may bestimulated in such a way to forget its past history. This memory erase effect, unexpected in a memristordevice, is closely related to the concept of fading memory from nonlinear system theory, and wasrecently confirmed through experiments conducted on a sample device.

Fabrication process of molecular memory circuits by nanoimprint lithography

We have utilized the nanoimprint lithography process described this paper to fabricate a rewritable, nonvolatile memory cell with an equivalent density of 6.4 Gbits/cm2. The architecture of the circuit was based on an 8x8 crossbar structure with an active molecular layer sandwiched between the top and bottom electrodes. A liftoff process was utilized to produce the top and bottom electrodes, made of Pt/Ti bilayers. The active molecular layer was deposited by the Languir-Blodgett technique. We proposed the use of a new class of nanoimprint resist formulated by dissolving a polymer in its monomer, such as poly(benzyl methacrylate) dissolved in benzyl methacrylate (~8%/92% wt). The new resist enabled us to achieve Pt /Ti lines of 40 nm in width and 130 nm in pitch, as described in this paper. Our overall nanofabrication process has the advantages of relatively low temperature (~70°C) and pressure (~500 psi or 4.5 MPa), both of which are critical to preserving the integrity of the molecular layer.

Memristor Emulators: A Note on Modeling

In a recent publication (Yi et al. 2011) elucidating a possible scheme to write information reliably onto a memory crossbar, Hewlett Packard Labs researchers employed a thyristor-based circuit to emulate the off-to-on switching behaviour of a titanium oxide memristor. The use of a thyristor device allowed them to test inexpensively and reliably the functionalities of the closed-loop crossbar write circuitry by using conventional CMOS components. From a device modeling point of view, however, it is worthy to point out that the aforementioned emulator is not a genuine memristor. The aim of this paper is to demonstrate with an in-depth mathematical analysis that the model of the thyristor does not fall into the class of memristors. The modelling approach adopted in this work may be a source of inspiration for researchers willing to check whether other devices or circuits may be classified as memristors.

Fading memory effects in a memristor for Cellular Nanoscale Network applications

CNN based analogic cellular computing is a unified paradigm for universal spatio-temporal computation with several applications in a large number of different fields of research. By endowing CNN with local memory, control, and communication circuitry, many different hardware architectures with stored programmability, showing an enormous computing power - trillion of operations per second may be executed on a single chip -, have been realized. The complex spatio-temporal dynamics emerging in certain CNN may lead to the development of more efficient information processing methods as compared to conventional strategies. Memristors exhibit a rich variety of nonlinear behaviours, occupy a negligible amount of integrated circuit area, consume very little power, are suited to a massively-parallel data flow, and may combine data storage with signal processing. As a result, the use of memristors in future CNN-based computing structures may improve and/or extend the functionalities of state-of-the art hardware architectures. This contribution provides a detailed analysis of the system-theoretic model of a tantalum oxide memristor, in view of its potential adoption for the implementation of synaptic operators in CNN architectures.