Rachid Bouchakour

Extraction of 3D parasitic capacitances in 90 nm and 22 nm NAND flash memories

In this paper we propose to study different ways to extract the values of parasitic capacitances in 90 nm and 22 nm NAND Flash memories. Indeed, these parasitic capacitances between cells in the array can modify applied polarizations and can disturb the functioning of the whole array. Their impact increases when the cell size is reduced, especially as the ultimate size of the 22 nm node is reached. We develop 3D TCAD simulations to extract parasitic capacitances as well as measurements on specific test structures or geometrical calculations, showing their increasing importance in the future technologies, especially for 22 nm node.

Modeling charge variation during data retention of MLC Flash memories

Abstract In this paper, we propose to model charge variation in Multi-Level Cells in NOR Flash memories. We first define a sensitivity-to-temperature factor to determine the number of involved mechanisms. Then, according to previous studies, we can use the Poole–Frenkel (PF) and/or the Fowler–Nordheim (FN) equations to model every charge loss, which we apply to our cells. We succeed in modeling our data retention measurements by superimposing these two phenomena, being, respectively preponderant at the beginning and at the end of the data retention measurements, as shown by the factor of sensitivity-to-temperature. We have then found a relationship between temperatures to evaluate our cells lifetime. We validate that the classical 1/T Arrhenius law is not the most appropriate and that a T model can be better. We also model a fictive charge gain by using a negative charge front displacement in the tunnel oxide. This study can easily be extended to any floating gate non-volatile memory.

A Full TCAD simulation and 3D parasitic capacitances extraction in 90nm NAND flash memories

In this paper we propose a way to study the degradation mechanism of ¿inhibited¿ cells during the cycling of ¿selected¿ cells in 90 nm NAND Flash memories. This degradation is a main issue in NAND Flash memories reliability. To explain this degradation, we first develop a 2D TCAD cell simulation to watch attentively what happens in the channel where measurements are impossible. Some phenomena are shown here which could begin to explain what occurs. Because of continual shrinking, coupling capacitances between cells in the array have a significant impact on the cell behaviour. The previous simulation can be completed by taking into account these 3D parasitic capacitances which have been extracted in a second time.

Heart rhythm characterization through induced physiological variables

Atrial fibrillation remains a major cause of morbi-mortality, making mass screening desirable and leading industry to actively develop devices devoted to automatic AF detection. Because there is a tendency toward mobile devices, there is a need for an accurate, rapid method for studying short inter-beat interval time series for real-time automatic medical monitoring. We report a new methodology to efficiently select highly discriminative variables between physiological states, here a normal sinus rhythm or atrial fibrillation. We generate induced variables using the first ten time derivatives of an RR interval time series and formally express a new multivariate metric quantifying their discriminative power to drive state variable selection. When combined with a simple classifier, this new methodology results in 99.9% classification accuracy for 1-min RR interval time series (n = 7,400), with heart rate accelerations and jerks being the most discriminant variables. We show that the RR interval time series can be drastically reduced from 60 s to 3 s, with a classification accuracy of 95.0%. We show that heart rhythm characterization is facilitated by induced variables using time derivatives, which is a generic methodology that is particularly suitable to real-time medical monitoring.

Design of an energy detector for heartbeat localization in ECG signals

Cardiovascular Diseases (CVD) causes as many deaths as cancer in Europe. A method to detect them consists in tracking the heartbeat rate from ECG signal. In this case, QRS complexes have to be localized and it is proposed here to use an energy detector to enable this. It can be integrated in an analog circuit and can also address low power and low cost applications such as consumer embedded electronics. Using a 0.35μm CMOS technology from AMS, the design of the analog multiplier cell required by the energy detector is presented here. It shows a voltage gain upper than 18 with a sufficient linearity for the targeted applications. Preliminary results of the full energy detector which mix Matlab computations and Eldo post-layout simulations show a detection rate about 98.8% for SNR upper than 0dB.

A partial tree vector quantizer dynamic element matching technique for audio Δ-Σ converters

Multi-bit Δ-Σ modulators are widely used in performing accurate, low-power, and low cost analogue-to-digital conversion (ADC). One of its major limits is the internal feedback digital-to-analogue converter (DAC) non-linearity. It generates unwanted tones and noise in the band of interest, which makes impossible to achieve the signal quality required in audio products. Authors have overcome this difficulty by designing mismatch-shaping techniques, also called Dynamic Element Matching (DEM). We propose in this paper a new vector-based DEM that we have added to a 4th order continuous-time ADC. It achieves good audio performances for a reasonable gate count.

A full 2D and 3D TCAD simulation of ultimate 22nm NAND Flash memories

In this paper we propose a way to study the ultimate technological node for Flash cell described in the International Technology Roadmap for Semiconductors (ITRS), corresponding to the 22nm feature size. We have first developed a 2D TCAD simulation of a 4-bit-NAND string based on classical microelectronics recipes, to validate the whole process conditions. To check the good behavior of our processed cells, we first evaluate the programmed and erased threshold voltages by electrically simulating the Drain Current versus Control Gate Voltage. Then we also investigate the impact of the short space between neighbor cells on disturb between cells inside the NAND string. We have developed a 3D TCAD simulation of a 3×3 array, based on the previous 2D process simulation, in order to extract the values of parasitic capacitances, disturbing the whole functioning of the array.

A Dual-Gate Memory Cell with Two Inter-Poly Oxides

A new dual-gate memory cell with two different inter-poly oxides is presented in this paper. This cell allows high density memory application and a cell programming only with the dual-gate without high bias on drain or source compared to standard electrical erasable and programmable read-only memory (EEPROM). Concept has been validated in an EEPROM standard technology from STMicroelectronics and allows a cell area reduction of above 48%. The specificity is to use a dual-gate to program the cell with two different ways of charge injection and perform the memory operations without high bias on drain and also without select transistor. Thus this cell can be shrunk more easily and its lifetime can be improved because the band to band tunneling stress due to high drain potential is eliminated. Moreover, this dual-gate cell can become an adjustable threshold voltage transistor.