Pierre Canet

Extraction of 3D parasitic capacitances in 90 nm and 22 nm NAND flash memories

In this paper we propose to study different ways to extract the values of parasitic capacitances in 90 nm and 22 nm NAND Flash memories. Indeed, these parasitic capacitances between cells in the array can modify applied polarizations and can disturb the functioning of the whole array. Their impact increases when the cell size is reduced, especially as the ultimate size of the 22 nm node is reached. We develop 3D TCAD simulations to extract parasitic capacitances as well as measurements on specific test structures or geometrical calculations, showing their increasing importance in the future technologies, especially for 22 nm node.

Modeling charge variation during data retention of MLC Flash memories

Abstract In this paper, we propose to model charge variation in Multi-Level Cells in NOR Flash memories. We first define a sensitivity-to-temperature factor to determine the number of involved mechanisms. Then, according to previous studies, we can use the Poole–Frenkel (PF) and/or the Fowler–Nordheim (FN) equations to model every charge loss, which we apply to our cells. We succeed in modeling our data retention measurements by superimposing these two phenomena, being, respectively preponderant at the beginning and at the end of the data retention measurements, as shown by the factor of sensitivity-to-temperature. We have then found a relationship between temperatures to evaluate our cells lifetime. We validate that the classical 1/T Arrhenius law is not the most appropriate and that a T model can be better. We also model a fictive charge gain by using a negative charge front displacement in the tunnel oxide. This study can easily be extended to any floating gate non-volatile memory.

A Full TCAD simulation and 3D parasitic capacitances extraction in 90nm NAND flash memories

In this paper we propose a way to study the degradation mechanism of ¿inhibited¿ cells during the cycling of ¿selected¿ cells in 90 nm NAND Flash memories. This degradation is a main issue in NAND Flash memories reliability. To explain this degradation, we first develop a 2D TCAD cell simulation to watch attentively what happens in the channel where measurements are impossible. Some phenomena are shown here which could begin to explain what occurs. Because of continual shrinking, coupling capacitances between cells in the array have a significant impact on the cell behaviour. The previous simulation can be completed by taking into account these 3D parasitic capacitances which have been extracted in a second time.

Access resistor modelling for EEPROM’s retention test vehicle

Abstract The electrical characteristic of EEPROM’s retention test vehicle presents two unexplained abnormalities in comparison with an individual cell’s measurement: the maximum drain–source current value and threshold voltage shift. We propose a simple electrical model based on access resistors in order to explain this behaviour. The model is presented, an extraction process is proposed and simulation results are compared with measurements. Then the model is used in order to predict the effect of a sector programmed inside an all erased memory array in order to simulate the threshold voltage shift observed with extrinsic cells during retention tests.

ReRAM ON/OFF resistance ratio degradation due to line resistance combined with device variability in 28nm FDSOI technology

Common problems with oxide-based Resistive RAM (ReRAM) are related to high variability in operating conditions and low yield. At array level, ReRAM memory cells suffer from different voltage drops seen across the cells due to the line resistances. Although research has taken steps to resolve these issues, variability combined with resistive paths remain an important characteristic for ReRAM. In this paper, the performance and reliability of ReRAM memory arrays is investigated in a 28nm FDSOI technology versus interconnects resistivity combined with device variability.

Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations

We demonstrate that infrared femtosecond laser pulses with intensity above the two-photon ionization threshold of crystalline silicon induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturally redistribute on both sides of the tunnel oxide until the electric field of the transistor is suppressed. This ability enables us to determine in a nondestructive, rapid and contactless way the flat band and the neutral threshold voltages of the tested device. The physical mechanisms including nonlinear ionization, quantum tunneling of free-carriers, and flattening of the band diagram are discussed for interpreting the experiments. The possibility to control the carriers in memory transistors with ultrashort pulses holds promises for fast and remote device analyses (reliability, security, and defectivity) and for considerable developments in the growing field o...

NVM cell degradation induced by femtosecond laser backside irradiation for reliability tests

In this paper we present the behavior of a single nonvolatile Flash floating gate memory cell when it is irradiated, from the backside, by femtosecond laser pulses. For the first time we show that the memory cell state can change using this type of stimulation. The measurements were carried out with an experimental setup with an ad hoc probe station built around the optical bench. We present the experimental results using different memory bias conditions to highlight the charge injection in the floating gate. Then, we study the cell degradation to check the state of the tunnel oxide and the drain-bulk junction. The aim is to understand the failure mechanisms and use this technique for accelerated reliability tests. Finally we report the experimental results achieved for different laser energies.

Optimization of the ATW Non-Volatile Memory for Connected Smart Objects

The development of new wireless devices is growing up, driven by the market of connected things for many applications: communications, cloud and health. In this scenario the current consumption of memory devices plays a key role. To save the battery of these devices, we need to develop the components that consume less and less. In this paper we propose to improve the performances of an original architecture of nonvolatile memory cell: the Asymmetrical Tunnel Window (ATW) cell. We compare here the standard Flash floating gate memory cell with the new proposed device, with an accurate experimental investigation of programming window and energy consumption. Moreover we optimized the ATW cell architecture by modifying the ratio of oxides lengths and thicknesses. Finally, we experimentally demonstrate an improvement of 4 times on the programming efficiency with respect the standard memory.

A full 2D and 3D TCAD simulation of ultimate 22nm NAND Flash memories

In this paper we propose a way to study the ultimate technological node for Flash cell described in the International Technology Roadmap for Semiconductors (ITRS), corresponding to the 22nm feature size. We have first developed a 2D TCAD simulation of a 4-bit-NAND string based on classical microelectronics recipes, to validate the whole process conditions. To check the good behavior of our processed cells, we first evaluate the programmed and erased threshold voltages by electrically simulating the Drain Current versus Control Gate Voltage. Then we also investigate the impact of the short space between neighbor cells on disturb between cells inside the NAND string. We have developed a 3D TCAD simulation of a 3×3 array, based on the previous 2D process simulation, in order to extract the values of parasitic capacitances, disturbing the whole functioning of the array.