Rachmad Vidya Wicaksana Putra

Rapid Prototyping Methodology of Lightweight Electronic Drivers for Smart Home Appliances

Many researches have been conducted in smart home topic. Mostly, they discussed on the specific aspect of application. On the other side, many applications still can be explored and attached into the system. Several main challenges in designing the application devices are system complexity, reliability, user friendliness, portability, and low power consumption. Thus, design of electronic driver is one of the key elements for overcoming these challenges. Moreover, the drivers have to comply the rules of smart home system, data protocol, and application purpose. Hence, we propose a rapid prototyping methodology on designing lightweight electronic drivers for smart home appliances. This methodology consists of three main aspects, namely smart home system understanding, circuitry concept, and programming concept. By using this method, functional and lightweight drivers can be achieved quickly without major changes and modifications in home electrical system. They can be remotely controlled and monitored anytime and from anywhere. For prototyping, we design several drivers to represent common electronic and mechanical based applications. Experimental results prove that the proposed design methodology can achieve the research target. Full Text: PDF DOI: http://dx.doi.org/10.11591/ijece.v6i5.11279

The refined mCBE algorithm for efficient constants multipliers architecture

In digital hardware, multiplication is frequently used for digital signal processing. We found that there are calculations which need several constants multipliers for the same data. Hence, we developed a multiplication from common binary expression (mCBE) algorithm in order to minimize the number of shifter-adder components to substitute multipliers. Actually, the first generation of the mCBE algorithm has been proposed before. However, it is optimally designed for DCT/IDCT processing. In this paper, we proposed the refined mCBE algorithm, the second generation (mCBEv2), to comply general constants multiplication characteristics. It is based on the constants binary decomposition and designed to establish an efficient multiplication architecture.

Design of low power mobile application for Smart Home

Design and implementation of smart home app is one of Internet-of-Things (IoT) topic which need to be explored more. Its major challenges are about capability on automatic adjustment with various operating system (OS), simple, efficient, compact and interactive. One of the most important issue is the battery consumption. Hence, this research aims is to develop an Android based low-power mobile application for smart home. This application design covers multi-control scheme (i.e. hard-control, soft-control and monitoring). Meanwhile, in order to investigate the battery consumption, we analyze few aspects, namely the effect of idle-active condition and difference color theme (i.e. red, green and blue).

Smart home platform based on optimized wireless sensor network protocol and scalable architecture

In this paper, we propose a smart home platform based on optimized wireless sensor network (WSN) protocol and scalable architecture. In this platform, system environment is divided into two main environments, indoor and outdoor. Outdoor environment uses internet-cloud system, while indoor environment uses WSN system. This scheme is also well known as Internet-of-Things (IoT) concept. Those two environments are connected to each other by using access point bridge. WSN system is established from efficient and scalable WSN components. Each component of WSN is designed to use an optimized protocol. WSN components are connected to each other in mesh topology in order to provide scalable architecture for further extension and changes. For outdoor environment, the existing internet-cloud system is used as infrastructure. Thus, this smart home platform can be monitored and controlled from smart phone, anytime and anywhere, as long as mobile data access is provided. For databasing implementation, SQLite database system is chosen because of its low cost and easy configuration. For system evaluation, several tests have been conducted to deliver the profile of proposed system.

Visible light communication system for wearable patient monitoring device

A visible light communication (VLC) system design for wearable patient monitoring device is proposed in this paper. This system consists of two devices, patient and coordinator devices. It is two-ways communication scheme. The downlink communication uses VLC, while the uplink uses infrared. It can help the doctor to monitor the patients condition. Moreover, VLC technology is considered to be safer and more comfortable to use. The device uses analog front-end (AFE) and processing module that includes software as the middleware layer. This software comprises MAC and PHY layers. MAC layer manages any kind of packet and transmission to PHY layer. Meanwhile, PHY layer is responsible as driver of transceiver (transmitter and receiver), error correction and data packet. Results of evaluation show the potential of the proposed system to be implemented in real life healthcare systems.

Analog filters design in VLC analog front-end receiver for reducing indoor ambient light noise

Visible Light Communication (VLC) technology in indoor implementation is challenged by ambient light and other lighting noise, such as fluorescent lamp and bulb. The ambient light could create a DC offset or signal with specific frequency range. Thus, we propose analog filters design in the VLC Analog Front-End (AFE) receiver that can eliminate the ambient light noise. The proposed design uses DC offset removal, incorporated with automatic and manual adjustment mode. In automatic mode, we design the analog filter using High Pass Filter (HPF) which have fc = 10Hz; meanwhile, in manual mode we design a reference circuit using potentiometer and differential amplifier for direct current blocking. For reducing signal interference from lamp flickering, the proposed design uses Band Stop Filter (BSF) which has fc = 100Hz. The experimental results, both simulation and realtime, show that our proposed design can reduce signal interference and ambient light. We also test the design using PWM and BPSK modulation to evaluate Bit Error Rate (BER) performance.

Hybrid multi System-on-Chip architecture: A rapid development design for high-flexibility system

In this paper, we propose a System-on-Chip (SoC) architecture that provides a high-flexibility system in a rapid development time. It is called Hybrid Multi SoC (H-MSoC). H-MSoC provides flexible SoC architecture that is easy to configure for physical and application layers development. These two aspects (physical and application layers) are dynamically designed and modified, hence it is important to consider and optimize their design methodology to support rapid SoC development. Physical layer development refers to Intellectual Property (IP) cores or hardware developments, while application layer development refers to user and interface application developments. H-MSoC is established from multi-SoC architectures which each SoC is localized and specified based on its development layer, either physical or application (hybrid). Physical layer development SoC is called Physical-SoC (Phy-SoC) and application layer development SoC is called Application-SoC (App-SoC). Phy-SoC and App-SoC are connected to each other via ethernet. Ethernet is chosen because of its flexibility, high-speed, and easiness for configuration. For prototyping purpose, we used LEON3 SoC as Phy-SoC and ZYNQ-7000 SoC as App-SoC. Proposed design has been proved in real time testing and achieved good performance.

The efficient mCBE algorithm and quantization numbers for multiplierless and low complexity DCT/IDCT Image Compression Architecture

This paper presents a multiplierless and low complexity of DCT/IDCT Image Compression Architecture by using two approaches. First, we propose multiplication decomposition by using our algorithm. This algorithm minimizes shifter-adder components to substitute multiplier efficiently. We named it as multiplication from Common Binary Expression (mCBE) Algorithm. Second, we propose alternative quantization numbers which can be simply implemented as shifter in digital hardware. These numbers can also retain good quality of compressed image compared to JPEG recommendation numbers. We named them as FathQuantz Numbers. Those improvements lead our proposed architecture becomes multiplierless and low complexity. The result states that our proposed 8-points 1D-DCT design has only 6 stages and 8-points 1D-IDCT design has only 7 stages. Here, we define 1 stage is equal to shifter or 2-inputs adder delay. So, by pipelining method, we can achieve high speed architecture with latency as trade off consideration. This design has been synthesized and it can speed up to 1.41ns crithical path delay (709.22MHz).

Optimized hardware algorithm for integer cube root calculation and its efficient architecture

Scientific applications, digital signal processing, and multimedia usually need to compute a large number of arithmetic operations. One of them is cube root operation. It is one of the fundamental arithmetic operation which is not received much attention. Because of its calculation complexity, cube root is difficult to implement in Field Programmable Gate Array (FPGA). Hence in this paper, we propose an optimized hardware algorithm for integer cube root calculation and its efficient architecture. Integer cube root calculation is computed by using 3-digits of binary number and iterative calculation. An optimized hardware algorithm idea is reducing computational complexity in factor generator unit. For design evaluations, we use 32-bit integer cube root architecture and simulate it with several test vectors. Evaluation results show us that the design architecture is valid. The design latency is defined by (N/3)+2, with N is bit-width of the design input. Hence, 32-bit design will be executed only in ((32+1)/3)+2 = 13 clock cycles. The design also has been synthesized for several FPGA implementation with promising results in area consumption and speed.

A register-free and homogenous architecture for square root algorithm

Square root calculation is an important operation in digital signal processing. A parallel architecture design for predictive square root algorithm is introduced. It is a parallel version of our previous research of iterative square root algorithm architecture. This parallel design can produce square root and remainder values directly without any additional corrections and without any registers. It computes each coupled bits of input in homogenous treatments which consist of CAG (compare and generate) mechanism, addition, subtraction, and concatenation. Hence, the architecture design is low complexity and pipelinable. The 32-bit input architecture has been synthesized for FPGA Altera Cyclone II EP2C35F672C6. It only needs 580 logic elements and register-free.