Radha Sundararajan

Diagnostics of ballistic electrons in a dc/rf hybrid capacitively coupled discharge

The energy distribution of ballistic electrons in a dc/rf hybrid parallel-plate capacitively coupled plasma reactor was measured. Ballistic electrons originated as secondaries produced by ion and electron bombardment of the electrodes. The energy distribution of ballistic electrons peaked at the value of the negative bias applied to the dc electrode. As that bias became more negative, the ballistic electron current on the rf substrate electrode increased dramatically. The ion current on the dc electrode also increased.

Measurement of electron temperatures and electron energy distribution functions in dual frequency capacitively coupled CF4/O2 plasmas using trace rare gases optical emission spectroscopy

Measurements of electron temperatures (Te) and electron energy distribution functions (EEDFs) in a dual frequency capacitively coupled etcher were performed by using trace rare gas optical emission spectroscopy (TRG-OES). The parallel plate etcher was powered by a high frequency (60 MHz) “source” top electrode and a low frequency (13.56 MHz) “substrate” bottom electrode. Te first increased with pressure up to ∼20 mTorr and then decreased at higher pressures. Increasing the bottom rf power resulted in higher electron temperatures. Electron temperatures in 90% CF4+10% O2 plasmas were similar to those in 80% CF4+20% O2 plasmas. EEDF exhibited bi-Maxwellian characteristics with enhanced high energy tail, especially at pressures >20 mTorr.

Addressing Dynamic Process Changes in High Volume Plasma Etch Manufacturing by Using Multivariate Process Control

Multivariate plasma etch modeling and control methodology are presented based on 65 and 45 nm gate production data utilizing wafer-to-wafer tool-level scatterometry. The selection of etch recipe variables for optimal control of wafer-to-wafer profile, within-wafer CD, and chamber-to-chamber CD is demonstrated and validated based on wafer-to-wafer, within wafer, and chamber matching experiments.

Advanced profile control and the impact of sidewall angle at gate etch for critical nodes

Gate patterning is critical to the final yield and performance of logic devices. Because of this, gate linewidth control is viewed by many as the most critical application for integrated metrology on etch systems. For several years, integrated metrology and wafer-level process control have been used in high volume manufacturing of 90 and 65nm polysilicon gate etch [1], [3], [17], [22]. These wafer-level CD control systems have shown the ability to significantly reduce CD variation. With gate linewidth under control (< 2nm 3σ wafer-to-wafer), the next parameter to impact gate electrical performance is side wall angle (SWA). SWA had not been considered a critical control parameter due to the difficulty of measurement with conventional scanning electron microscope (SEM). With scatterometry, SWA measurement of litho and etch profiles are included with the critical dimension (CD) measurements. Recently, it has become visible that the polysilicon SWA correlates to electrical device parameters, and is thus, an important parameter to control. This paper will examine the current relationship between litho and etch profile control, determine potential limitations for future technology nodes, and introduce novel etch process control techniques based on multiple input multiple output (MIMO) modeling.

Effect of electron energy distribution functions on plasma generated vacuum ultraviolet in a diffusion plasma excited by a microwave surface wave

Plasma generated vacuum ultraviolet (VUV) in diffusion plasma excited by a microwave surface wave has been studied by using dielectric-based VUV sensors. Evolution of plasma VUV in the diffusion plasma as a function of the distance from the power coupling surface is investigated. Experimental results have indicated that the energy and spatial distributions of plasma VUV are mainly controlled by the energy distribution functions of the plasma electrons, i.e., electron energy distribution functions (EEDFs). The study implies that by designing EEDF of plasma, one could be able to tailor plasma VUV in different applications such as in dielectric etching or photo resist smoothing.

Increased uniformity control in a 45nm polysilicon gate etch process

As die feature sizes continue to decrease, advanced process control has become essential for controlling profile and CD uniformity across the wafer. Gate CD variation must be suppressed by process optimization of lithography, photoresist trim, and gate etch in order to achieve the demanding CD control tolerances. Currently, APC is used in the lithography and etch processes for within wafer (WiW) and wafer-to-wafer (W2W) CD control. APC can make improvements in process results, but there is still variation that needs to be further reduced. Analysis of the current lithography edge CD showed that the variation trend transferred to the post-etch edge CD measurement. Additionally, the etch process created variation in the edge CD independently of the lithography process. It can be challenging to compensate for the variations in the etch process and such compensations degrade through pitch OPC. Multivariable control of the etch process can reduce the need for compensations and, consequently, through pitch variation. A DOE was designed and run using the production etch process as a center reference for the creation of a WiW etch control model. This control model was then tested with a MATLAB based simulation program that simulates the etch production process sequence and the ability to target the edge CD. This demonstration shows that through rigorous methodology a multivariate model can be created for targeting both center CD (W2W) and edge CD (WiW) control, providing an opportunity at etch to reduce compensation for the etch variations at litho, and to provide the capability at etch to compensate for both litho and etch uniformity changes by wafer.

Common APC architecture for 200- and 300-mm etch

New 300mm facilities are decreasing start-up risks by developing new processes on 200mm equipment and transferring the process and manufacturing methods to the 300mm line. 200mm factories have stable processes, equipment and manufacturing methods. Leveraging a common Advanced Process Control (APC) architecture, both semiconductor manufacturers and equipment manufacturers have the ability to extend 200mm equipment capability, and transfer successful APC methods direct. Having a common tool-level APC on both 200mm and 300mm etch equipment, has proven valuable for TEL. Starting with fault detection and process control on 200mm equipment provides for rapid learning and qualification of the APC architecture and interfaces. When transferring the process and manufacturing methods that include APC to 300mm equipment, factories can efficiently ramp up new processes, and focus efforts in areas of high risk that need integrated fault detection. Etch process equipment provides the ultimate challenge due to the lack of physical process models. This requires extensive measurements of equipment and plasma state, followed by the development of empirical models to correlate equipment related state to the process state. The etch process requires chambers to be cleaned and consumable parts replaced, adding a large variable that must be included to make the models robust in high-volume manufacturing. Optimum productivity requires multiplexing 3 or 4 chambers running the same process. Chambers must produce matched process results, while allowing different clean cycles for flexibility of maintenance. Multivariate analysis, relating the equipment and plasma state to the wafer state, is required. A strategy that includes 200mm equipment in parallel with 300mm development supports customer legacy equipment improvements while providing a platform for 300mm APC applications that will extend pas current 200mm tool capability as new processes and manufacturing methods are developed. TELs Etch APC product allows for equipment integration of real-time data, events, external sensors, and integrated metrology.