Asao Yamashita

Feedforward of mask open measurements on an integrated scatterometer to improve gate linewidth control

As feature geometries decrease, the budgeted error for process variations decreases as well. Keeping these variations within budget is especially important in the area of gate linewidth control. Because of this, wafer-to-wafer control of gate linewidth becomes increasingly necessary. This paper shows results from 300 mm wafers with 90 nm technology that were trimmed during the gate formation process on an etch platform. After the process that opened the gate hard mask and stripped the resist, the wafers were measured using both an integrated scatterometer and a stand-alone CD-SEM. The measurements were then used to determine the appropriate amount to be trimmed by the Chemical Oxide Removal (COR) chamber that is also integrated onto the etch system. After the wafers were trimmed and etched, they were again measured on the integrated scatterometer and stand-alone CD-SEM. With the CD-SEM as the Reference Measurement System (RMS), Total Measurement Uncertainty (TMU) analysis was used to optimize the Optical Digital Profilometry (ODP) model, thus facilitating a significant reduction in gate linewidth variation. Because the measurement uncertainty of the scatterometer was reduced to a level approaching or below that of the RMS, an improvement to TMU analysis was developed. This improvement quantifies methods for determining the measurement uncertainty of the RMS under a variety of situations.

Addressing Dynamic Process Changes in High Volume Plasma Etch Manufacturing by Using Multivariate Process Control

Multivariate plasma etch modeling and control methodology are presented based on 65 and 45 nm gate production data utilizing wafer-to-wafer tool-level scatterometry. The selection of etch recipe variables for optimal control of wafer-to-wafer profile, within-wafer CD, and chamber-to-chamber CD is demonstrated and validated based on wafer-to-wafer, within wafer, and chamber matching experiments.

Advanced profile control and the impact of sidewall angle at gate etch for critical nodes

Gate patterning is critical to the final yield and performance of logic devices. Because of this, gate linewidth control is viewed by many as the most critical application for integrated metrology on etch systems. For several years, integrated metrology and wafer-level process control have been used in high volume manufacturing of 90 and 65nm polysilicon gate etch [1], [3], [17], [22]. These wafer-level CD control systems have shown the ability to significantly reduce CD variation. With gate linewidth under control (< 2nm 3σ wafer-to-wafer), the next parameter to impact gate electrical performance is side wall angle (SWA). SWA had not been considered a critical control parameter due to the difficulty of measurement with conventional scanning electron microscope (SEM). With scatterometry, SWA measurement of litho and etch profiles are included with the critical dimension (CD) measurements. Recently, it has become visible that the polysilicon SWA correlates to electrical device parameters, and is thus, an important parameter to control. This paper will examine the current relationship between litho and etch profile control, determine potential limitations for future technology nodes, and introduce novel etch process control techniques based on multiple input multiple output (MIMO) modeling.

Increased uniformity control in a 45nm polysilicon gate etch process

As die feature sizes continue to decrease, advanced process control has become essential for controlling profile and CD uniformity across the wafer. Gate CD variation must be suppressed by process optimization of lithography, photoresist trim, and gate etch in order to achieve the demanding CD control tolerances. Currently, APC is used in the lithography and etch processes for within wafer (WiW) and wafer-to-wafer (W2W) CD control. APC can make improvements in process results, but there is still variation that needs to be further reduced. Analysis of the current lithography edge CD showed that the variation trend transferred to the post-etch edge CD measurement. Additionally, the etch process created variation in the edge CD independently of the lithography process. It can be challenging to compensate for the variations in the etch process and such compensations degrade through pitch OPC. Multivariable control of the etch process can reduce the need for compensations and, consequently, through pitch variation. A DOE was designed and run using the production etch process as a center reference for the creation of a WiW etch control model. This control model was then tested with a MATLAB based simulation program that simulates the etch production process sequence and the ability to target the edge CD. This demonstration shows that through rigorous methodology a multivariate model can be created for targeting both center CD (W2W) and edge CD (WiW) control, providing an opportunity at etch to reduce compensation for the etch variations at litho, and to provide the capability at etch to compensate for both litho and etch uniformity changes by wafer.