Merritt Funk

Diagnostics of ballistic electrons in a dc/rf hybrid capacitively coupled discharge

The energy distribution of ballistic electrons in a dc/rf hybrid parallel-plate capacitively coupled plasma reactor was measured. Ballistic electrons originated as secondaries produced by ion and electron bombardment of the electrodes. The energy distribution of ballistic electrons peaked at the value of the negative bias applied to the dc electrode. As that bias became more negative, the ballistic electron current on the rf substrate electrode increased dramatically. The ion current on the dc electrode also increased.

Feedforward of mask open measurements on an integrated scatterometer to improve gate linewidth control

As feature geometries decrease, the budgeted error for process variations decreases as well. Keeping these variations within budget is especially important in the area of gate linewidth control. Because of this, wafer-to-wafer control of gate linewidth becomes increasingly necessary. This paper shows results from 300 mm wafers with 90 nm technology that were trimmed during the gate formation process on an etch platform. After the process that opened the gate hard mask and stripped the resist, the wafers were measured using both an integrated scatterometer and a stand-alone CD-SEM. The measurements were then used to determine the appropriate amount to be trimmed by the Chemical Oxide Removal (COR) chamber that is also integrated onto the etch system. After the wafers were trimmed and etched, they were again measured on the integrated scatterometer and stand-alone CD-SEM. With the CD-SEM as the Reference Measurement System (RMS), Total Measurement Uncertainty (TMU) analysis was used to optimize the Optical Digital Profilometry (ODP) model, thus facilitating a significant reduction in gate linewidth variation. Because the measurement uncertainty of the scatterometer was reduced to a level approaching or below that of the RMS, an improvement to TMU analysis was developed. This improvement quantifies methods for determining the measurement uncertainty of the RMS under a variety of situations.

Integrated scatterometry in high-volume manufacturing for polysilicon gate etch control

For several years, integrated scatterometry has held the promise of wafer-level process control. While integrated scatterometry on lithography systems is being used in manufacturing, production implementation on etch systems is just beginning to occur. Because gate patterning is so important to yield, gate linewidth control is viewed by many as the most critical application for integrated scatterometry on etch systems. IBM has implemented integrated scatterometry on its polysilicon gate etch systems to control gate linewidth for its 90 nm node SOI-based microprocessors in its 300 mm manufacturing facility. This paper shows the performance of the scatterometry system and the equipment-based APC system used to control the etch process. Some of the APC methodology is described, as well as sampling strategies, throughput considerations, and scatterometry models. Results reveal that the scatterometry measurements correlate well to CD-SEM measurements before and after etch, and also correlate to electrical measurements. Finally, the improvement in linewidth distribution following the implementation of feedforward and feedback control in full manufacturing is shown.

Measurement of electron temperatures and electron energy distribution functions in dual frequency capacitively coupled CF4/O2 plasmas using trace rare gases optical emission spectroscopy

Measurements of electron temperatures (Te) and electron energy distribution functions (EEDFs) in a dual frequency capacitively coupled etcher were performed by using trace rare gas optical emission spectroscopy (TRG-OES). The parallel plate etcher was powered by a high frequency (60 MHz) “source” top electrode and a low frequency (13.56 MHz) “substrate” bottom electrode. Te first increased with pressure up to ∼20 mTorr and then decreased at higher pressures. Increasing the bottom rf power resulted in higher electron temperatures. Electron temperatures in 90% CF4+10% O2 plasmas were similar to those in 80% CF4+20% O2 plasmas. EEDF exhibited bi-Maxwellian characteristics with enhanced high energy tail, especially at pressures >20 mTorr.

Addressing Dynamic Process Changes in High Volume Plasma Etch Manufacturing by Using Multivariate Process Control

Multivariate plasma etch modeling and control methodology are presented based on 65 and 45 nm gate production data utilizing wafer-to-wafer tool-level scatterometry. The selection of etch recipe variables for optimal control of wafer-to-wafer profile, within-wafer CD, and chamber-to-chamber CD is demonstrated and validated based on wafer-to-wafer, within wafer, and chamber matching experiments.

Direct current-self-sustained non-ambipolar plasma at low pressure

For decades, non-ambipolar diffusion has been observed and studied in laboratory plasmas that contain a double layer. However, self-sustained non-ambipolar plasma has yet to be demonstrated. This article reports the method and results for achieving such a condition at low pressure, with a wide power range (as low as 6 W). The findings reveal that to achieve self-sustained non-ambipolar plasma, both the balance between electron and ion heating and the space-potential gradient are critical. The plasma reactor developed in this work has potential applications that include microelectronic surface processing and space propulsion, via space-charge-neutral plasma-beam thruster, when operated in the high power regime.

Advanced profile control and the impact of sidewall angle at gate etch for critical nodes

Gate patterning is critical to the final yield and performance of logic devices. Because of this, gate linewidth control is viewed by many as the most critical application for integrated metrology on etch systems. For several years, integrated metrology and wafer-level process control have been used in high volume manufacturing of 90 and 65nm polysilicon gate etch [1], [3], [17], [22]. These wafer-level CD control systems have shown the ability to significantly reduce CD variation. With gate linewidth under control (< 2nm 3σ wafer-to-wafer), the next parameter to impact gate electrical performance is side wall angle (SWA). SWA had not been considered a critical control parameter due to the difficulty of measurement with conventional scanning electron microscope (SEM). With scatterometry, SWA measurement of litho and etch profiles are included with the critical dimension (CD) measurements. Recently, it has become visible that the polysilicon SWA correlates to electrical device parameters, and is thus, an important parameter to control. This paper will examine the current relationship between litho and etch profile control, determine potential limitations for future technology nodes, and introduce novel etch process control techniques based on multiple input multiple output (MIMO) modeling.

Effect of electron energy distribution functions on plasma generated vacuum ultraviolet in a diffusion plasma excited by a microwave surface wave

Plasma generated vacuum ultraviolet (VUV) in diffusion plasma excited by a microwave surface wave has been studied by using dielectric-based VUV sensors. Evolution of plasma VUV in the diffusion plasma as a function of the distance from the power coupling surface is investigated. Experimental results have indicated that the energy and spatial distributions of plasma VUV are mainly controlled by the energy distribution functions of the plasma electrons, i.e., electron energy distribution functions (EEDFs). The study implies that by designing EEDF of plasma, one could be able to tailor plasma VUV in different applications such as in dielectric etching or photo resist smoothing.

Propagation and scattering in a microwave plasma chamber

The paper presents the analysis of propagation and scattering in a microwave plasma chamber. The chamber consists of a looped circular waveguide with the TE11 mode excited by the TE10 mode from a linear rectangular waveguide. The microwave power extracted through a slit along the cavity wall that is lined by quartz permeates the oxygen injected in the center and ionized by 50,000 volts hence creating plasma. The complexity of the scattering of the field through the quartz and propagating in the plasma provides several challenges to obtaining a uniform field distribution within the chamber. A nonlinear Drude model of the plasma in CST (Computer Simulation Technology) has been developed to analyze the scattered field in the plasma region.

Increased uniformity control in a 45nm polysilicon gate etch process

As die feature sizes continue to decrease, advanced process control has become essential for controlling profile and CD uniformity across the wafer. Gate CD variation must be suppressed by process optimization of lithography, photoresist trim, and gate etch in order to achieve the demanding CD control tolerances. Currently, APC is used in the lithography and etch processes for within wafer (WiW) and wafer-to-wafer (W2W) CD control. APC can make improvements in process results, but there is still variation that needs to be further reduced. Analysis of the current lithography edge CD showed that the variation trend transferred to the post-etch edge CD measurement. Additionally, the etch process created variation in the edge CD independently of the lithography process. It can be challenging to compensate for the variations in the etch process and such compensations degrade through pitch OPC. Multivariable control of the etch process can reduce the need for compensations and, consequently, through pitch variation. A DOE was designed and run using the production etch process as a center reference for the creation of a WiW etch control model. This control model was then tested with a MATLAB based simulation program that simulates the etch production process sequence and the ability to target the edge CD. This demonstration shows that through rigorous methodology a multivariate model can be created for targeting both center CD (W2W) and edge CD (WiW) control, providing an opportunity at etch to reduce compensation for the etch variations at litho, and to provide the capability at etch to compensate for both litho and etch uniformity changes by wafer.