Radu Muresan

Protection Circuit against Differential Power Analysis Attacks for Smart Cards

In this paper, we present a circuit that protects smart cards against differential power analysis attacks. The circuit is based on a current flattening technique, is designed using a standard 0.18-mum CMOS technology, and can be integrated on the same die or in the same package with the smart card microcontroller. We evaluate the current flattening performance and the effectiveness of the protection against differential power analysis attacks. Our analysis is based on transistor-level simulations in Cadence environment using experimental current traces collected from an 8-bit microcontroller for smart cards executing DES encryptions. The proposed circuit effectively protects against differential power analysis attacks with small chip area overhead and limited increased power consumption during the encryption cycles.

Fuzzy control of semi-active automotive suspensions

This paper presents a new fuzzy controller for semi-active vehicle suspension systems, which has a significantly fewer number of rules in comparison to existing fuzzy controllers. The proposed fuzzy controller has only nine fuzzy rules, whose performance is equivalent to the existing fuzzy controller with 49 fuzzy rules. The proposed controller with less number of fuzzy rules will be more feasible and cost-efficient in hardware implementation. For comparison, a linear quadratic regulator controlled semi-active suspension, and a passive suspension are also implemented and simulated. Simulation results show that the ride comfort and road holding are improved by 28% and 31%, respectively, with the fuzzy controlled semi-active suspension system, in comparison to the linear quadratic regulator controlled semi-active suspension.

On-chip current flattening circuit with dynamic voltage scaling

This paper presents the circuit-level implementation for a current flattening system designed to control the power-supply current and to protect cryptosystems from power analysis attacks. When required, the proposed circuit dynamically controls the power consumption by injecting an extra current and by scaling the power-supply voltage. The circuit can be integrated on the same chip with a cryptographic processor. In this way the power-supply current has little meaningful information for a side-channel attack. The proposed circuit has been designed in a 0.18 mum CMOS technology and operates with a nominal 1.8-V power supply

An integrated current flattening module for embedded cryptosystems

In embedded cryptosystems, the variation of current or power consumption might be the point of attack on confidentiality because of the dependency of power consumption on the data and algorithms. This paper presents a real-time current flattening module that controls dynamically the power consumption of a cryptosystem. The module together with specialized cryptographic hardware can be integrated on the same chip. In this way, the output current of the cryptographic system has little discernable information for a side-channel attack. The real-time current flattening module is designed in this paper using 0.18 /spl mu/m CMOS technology and operates at 1.8 V power supply.

Current consumption dynamics at instruction and program level for a VLIW DSP processor

The paper describes a new methodology for analyzing low-level current dynamics at the instruction level and the program level for a VLIW DSP processor core. An efficient methodology for software power analysis is presented, which, unlike other research supports dynamic current analysis and complex VLIW processor cores. Analysis of high bank register allocation, equivalent functional construct usage, and program-based current, power, and energy is presented. The basic principles and methods developed throughout this research are general and applicable to complex pipelined processors. The research is important for analyzing and designing secure power-efficient DSP embedded applications.

Integrated capacitor switchbox for security protection

This paper presents a capacitor bank and a switch box as an on-chip Power Analysis Attack (PAA) countermeasure for embedded systems. This approach allows for the decoupling and isolation of individual sensitive and non-sensitive modules from the power supply. The random connections made by the switch box between functional modules and charged capacitors also contribute to the decorrelation between collected traces and the operations being performed by sensitive modules. A DC-DC converter is also present to generate a stable and suitable supply voltage. The design was simulated using 65 nm CMOS technology in Cadence, with an implementation of the Advanced Encryption Standard (AES) Sbox as a test module. Initial results showed a reduction in the effectiveness of the Correlation Power Analysis (CPA) attack on the Sbox module.

FPGA based real-time adaptive fuzzy logic controller

Fuzzy logic based control systems provide a simple and efficient method to control highly complex and imprecise systems. However, the lack of a simple hardware design that is capable of modifying the fuzzy controllers parameters to adapt for any changes in the operation environment, or behavior of the plant system limits the applicability of fuzzy based control systems in the automotive and industrial environments. The design and implementation of an FPGA based fuzzy logic controller, that allows real-time modification of its membership functions and rule base is introduced in this paper. The development of the controllers architecture is carried out on a National Instruments Intelligent DAQ board (PCI-7833R) with a reconfigurable Xilinx Virtex-II FPGA. The proposed design combines the performance advantages of existing static FPGA based fuzzy control architectures, with the flexibility and ease of implementation of conventional micro-controllers and general purpose processors. To test the efficiency of the controller and its ability to stabilize a highly dynamic system, a semi-active suspension system was developed. Simulation results for the proposed FPGA controller showed a 56% characteristic enhancement over the standard passive suspension system.

Low-voltage wide-range built-in current sensing for system-on-chip applications

This paper presents a low-voltage on-chip current sensor that is well suited for cryptosystem applications, as well as testing, and battery lifetime improvement. The sensing method is based on an improved current mirror with a compensating circuit and a dynamic control loop that provides wide range and high linearity while introducing a small voltage drop. The voltage drop across the sensor remains below 60 mV (less than a single VDSsat) for a wide current range of 0.5 to 10 mA and the linearity is better than 98%. The total power dissipation for 5 mA is 700 muW. The proposed circuit has been designed and simulated in 0.18-mum CMOS process with 1.8 V supply

Instantaneous current modeling in a complex VLIW processor core

Measuring and modeling instantaneous current consumption or current dynamics of a processor is important in embedded system designs, wireless communications, low-energy mobile computing, security of communications, and reliability. In this paper, we introduce a new instruction-level based macromodeling approach for instantaneous current consumption in a complex processor core along with new instantaneous current measurement techniques at the instruction and program level. Current consumption and voltage supply waveforms of a processor core were acquired by a sampling oscilloscope through an external interrupt-based setup. Accurate measurements of current, power and energy consumption at the instruction, block, or program level were obtained from analyzing the stored current and voltage waveforms. The current simulation methodology uses elementary functions called atomic functions to approximate the instantaneous current consumption at the instruction level. Based on these atomic functions, a simulated instantaneous current waveform at the program level was built. First, a base waveform of the current simulation was generated by the use of four basic current superposition principles. Secondly, a final waveform of the simulated current was generated from the base waveform by applying a factorial adjustment as a function of the instruction parallelism and sequencing. Step-by-step modeling procedures with numerical examples are presented. The model captured 98% of the variation of the instantaneous current for six complex applications, with an average RMS error of less than 2.2% of the average measured mean. Energy estimates obtained by the use of the simulated current waveforms were within 1.4% of the measured values. This research is important, since for the first time highly accurate instruction-based models of instantaneous current and power for complex processor cores have been developed.

A dynamic programming approach to complex allocation in a DSP pipelined processor

This paper describes a deterministic non-serial dynamic programming technique applicable to a code optimization problem for the Star Core 140 (SC140) DSP processor. The code optimization problem analyzed is an optimal register allocation problem that minimizes the expected number of execution sets with a two-word prefix for the SC140 core applications based on two probabilistic allocation policies. We introduce two basic algorithms, a linear bridging algorithm and a non-linear bridging algorithm (supporting loops), that solve the specific register allocation problem for an assembly language code block. All algorithms and methods are applied to a variety of SC140 assembly code applications. The optimized assembly language codes generated show an average of 68%, improvement in overheads and an average of 4.44% code size reduction at a very small increase in the CPU time costs. The basic principles and methods developed throughout this research are general and are applicable to other pipelined processors.