Raf Roovers

A 12 b 50 M sample/s cascaded folding and interpolating ADC

The architecture of this 12 b ADC is based on a three-stage conversion, using cascaded folding and interpolating techniques. Compared to other multi-stage ADC architectures, folding and interpolating ADCs are based on non-linear analog pre-processing. This architecture is an attractive solution for high-resolution ADCs, as extremely linear circuit topologies are not required. To increase the resolution of folding and interpolating ADCs above the published 8 b examples, without raising the number of parallel input stages or the number of comparators in the fine-comparator, a cascaded folding and interpolating architecture is introduced. The ADC achieves 64 dB signal-to-noise ratio (SNR) and 75 dB spurious-free dynamic range (SFDR), while quantizing a 15 MHz full-scale input signal at 50 MSample/s. The 7.0 mm/sup 2/ ADC is fabricated in a 13 GHz, 1 /spl mu/m BiCMOS process and dissipates 300 mW from a single 5.0 V supply. The device is mounted in a standard 44-pin plastic package.

Mismatch characterization of small size MOS transistors

A test chip for characterization of transistor mismatch in a standard 1.2 /spl mu/m CMOS technology is presented. A new algorithm for matching parameter extraction has been used. Mismatch parameters based on measurements on 12000 nMOS and 10000 pMOS transistors have been extracted. It is observed that the threshold voltage mismatch linear dependency on the inverse of the square root of the effective channel area no longer holds for transistors of 1.2 /spl mu/m channel length. An extended model based on the physical causes of threshold voltage mismatch is proposed.

A 2.5-V 12-b 54-Msample/s 0.25-/spl mu/m CMOS ADC in 1-mm/sup 2/ with mixed-signal chopping and calibration

This paper describes a two-step analog-to-digital converter (ADC) with a mixed-signal chopping and calibration algorithm. The ADC consists primarily of analog blocks, which do not suffer from the matching limitations of active devices. The offset on two residue amplifiers limits the accuracy of the ADC. Background digital offset extraction and analog compensation is implemented to continuously remove the offset of these critical analog components. The calibrated two-step ADC achieves -70 dB THD in the Nyquist band, with a 2.5-V supply. The ADC is realized in standard single-poly 5-metal 0.25-/spl mu/m CMOS, measures 1.0 mm/sup 2/, and dissipates 295 mW.

A continuous-time /spl Sigma//spl Delta/ ADC with increased immunity to interferers

Receivers are being digitized in a quest for flexibility. Analog filters and programmable gain stages are being exchanged for digital processing at the price of a very challenging ADC. This paper presents an alternative solution where the filter and programmable gain functionality is integrated into a /spl Sigma//spl Delta/ ADC. The novel filtering ADC is realized by adding a high-pass feedback path to a conventional /spl Sigma//spl Delta/ ADC while a compensating low-pass filter in the forward path maintains stability. As such, the ADC becomes highly immune to interferers even if they exceed the maximum allowable input level for the wanted channel. As a consequence, the ADC input range can be programmed dynamically to the level of the wanted signal only. This results in an input-referred dynamic range of 89 dB in 1-MHz bandwidth and an intentionally moderate output signal-to-noise-and-distortion ratio of 46-59 dB (depending on the programmed gain). The merged functionality enables a better overall power/performance balance for the receiver baseband. The design consumes less than 2 mW and active area is 0.14 mm/sup 2/ in a 0.18-/spl mu/m digital CMOS technology.

A 1-GHz single-chip quadrature modulator

The design of an integrated quadrature modulator for a 800-MHz to 1-GHz frequency range is presented. It is shown that this modulator achieves a phase error of less than +or-3 degrees without any trimming or tuning. This performance was achieved by reducing the number of building blocks and keeping a symmetrical transistor structure even in the layout. To overcome the amplitude difference of the phase-shifted signals, a modulator principle is used rather than a multiplier principle. The circuit was implemented in a bipolar transistor array with an f/sub T/ of 9 GHz. >

An IF-to-Baseband

A single-bit fifth-order complex continuous-time IF-to-baseband SigmaDelta modulator for AM/FM/IBOC receivers is presented. The input IF is 10.7 MHz and the sampling frequency is 41.7 MHz. The modulator achieves a dynamic range of 118dB in AM mode (3 kHz BW), 98dB in FM mode (200 kHz BW), and 86dB in IBOC mode (500 kHz BW). The modulators high dynamic range enables the realization of an AM radio receiver without a VGA and without an AM channel-selection filter, thereby reducing system complexity and cost. The elimination of the VGA also improves the sensitivity and the overall noise figure of the receiver. The modulators spurious free dynamic range is 88 dB in the bandwidth from 25 to 525 kHz. The IM2 distance is 92 dB, and the IM3 distance is 91 dB. The ADC was fabricated in a one-poly five-metal 0.18-mum CMOS process with an active area of 6.0mm2. It consumes 210 mW from a 1.8-V supply

\Sigma \Delta

A 100-MHz 8 bit A/D (analog-to-digital) converter realized in a standard 1.5 /spl mu/m CMOS technology is presented. By implementing a current interpolating technique, the input capacitance has been reduced compared to that of flash converter. As this current interpolating circuit is an analog preprocessing circuit, the speed is mainly determined by the comparators and the digital decoding logic. A novel high-speed, single-clock-phase current latch has been developed. The latch is combined with a decoder and error correcting circuit in true single clock phase logic, which allows sampling frequencies up to 100 MHz.

Modulator for AM/FM/IBOC Radio Receivers With a 118 dB Dynamic Range

A 175 Ms/s A/D converter with a latency of one clock cycle is designed in a 0.7 /spl mu/m digital CMOS technology. The resolution of the converter is 6 b while the power dissipation is only 160 mW. The A/D converter architecture is based on a continuous time analog preprocessing topology. A continuous time current interpolation circuit is implemented. The performance of the A/D converter is ruled by a tradeoff between speed, power, and accuracy.

A 100 MHz 8 bit CMOS interpolating A/D converter

A new subsite stepped multiresistor test structure is introduced. This test structure is used for studying and improving small resistance mismatch patterns in resistor ladders for high-resolution analog-to-digital converter applications. By utilizing wafer prober subsite movements and contact pad cross connections in the test structures, in combination with a Kelvin measurement method and dedicated statistical data evaluation technique, this approach enables identification of very small (<0.05%) systematic resistance mismatch patterns in realistic high- precision resistor ladder implementation. The most disturbing mismatch pattern was found to be caused by mechanical stress from the resistor ladder head layout, while others are attributed to decananometer scale reticle writing artefacts.

A 175 Ms/s, 6 b, 160 mW, 3.3 V CMOS A/D converter

A statistical approach for evaluating the stochastic mismatching between two identically designed elements on the same chip is discussed. An approach to determine accurate matching parameters for a specific pair of devices and to obtain realistic worst case parameters for the area dependency model is presented. The approach is demonstrated by applying it to measured transistor threshold voltage mismatching data for a 0.7 /spl mu/m CMOS technology.