Maarten Vertregt

Transistor matching in analog CMOS applications

This paper gives an overview of MOSFET mismatch effects that form a performance/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit design is discussed. Mismatch effects gain importance as critical dimensions and CMOS power supply voltages decrease.

A 6-b 1.6-Gsample/s flash ADC in 0.18-/spl mu/m CMOS using averaging termination

A 1.6 Gsample/s 6b flash analog-to-digital converter in 0.18 /spl mu/m CMOS is for storage read channels. The array of amplifiers and averaging resistors is terminated with less overrange while maintaining full-scale linearity. Consuming 340 mW, it achieves 5.7 effective bits at DC and 5 effective bits at 660 MHz.

A 2.5-V 12-b 54-Msample/s 0.25-/spl mu/m CMOS ADC in 1-mm/sup 2/ with mixed-signal chopping and calibration

This paper describes a two-step analog-to-digital converter (ADC) with a mixed-signal chopping and calibration algorithm. The ADC consists primarily of analog blocks, which do not suffer from the matching limitations of active devices. The offset on two residue amplifiers limits the accuracy of the ADC. Background digital offset extraction and analog compensation is implemented to continuously remove the offset of these critical analog components. The calibrated two-step ADC achieves -70 dB THD in the Nyquist band, with a 2.5-V supply. The ADC is realized in standard single-poly 5-metal 0.25-/spl mu/m CMOS, measures 1.0 mm/sup 2/, and dissipates 295 mW.

A 25-Ms/s 8-bit CMOS A/D converter for embedded application

The design of an 8-bit CMOS A/D converter is described which is intended for embedded operation in VLSI chips for video applications. The requirements on accuracy are analyzed and a comparator circuit is shown which realizes a high bandwidth. The full-flash architecture operates on wideband signals like CVBS in television systems. The A/D converter core measures 2.8 mm/sup 2/ in a 1 /spl mu/m CMOS process. The embedded operation of the A/D converter is illustrated on a video line-resizing chip. >

A 15-bit 30-MS/s 145-mW three-step ADC for imaging applications

A 15-bit 30 MS/s three-step ADC for imaging applications is presented with a peak-to-peak signal to rms noise ratio of 84 dB. The offsets of the residue amplifiers are independently background calibrated. The ADC is realized in single poly, 0.18 /spl mu/m CMOS, measures 1.4 mm/sup 2/ and dissipates 145 mW from 1.8 V and 3.3 V supplies.

A 25 mu m/sup 2/ bulk full CMOS SRAM cell technology with fully overlapping contacts

The authors describe a 25.2 mu m/sup 2/ bulk full CMOS SRAM cell for application in high-density static memories fabricated in a 14-mask process using minimum dimensions of 0.5 mu m at a comparatively relaxed 1.2 mu m pitch. A very aggressive n/sup +//p/sup +/ spacing and a fully overlapping contact technology are the key elements used to achieve a competitive cell area. The functionality of the cell was shown on a 1 kb test memory.<<ETX>>

Assessment of the merits of CMOS technology scaling for analog circuit design

Key device parameters such as drain current, transconductance, current factor, capacitance, etc. are linked to typical analog circuit level performance criteria, as a function of the CMOS technology node. Subsequently, speed and power implications for an analog-to-digital converter building block are estimated. Significant power efficiency improvements are predicted as a result of scaling to deep sub-micron technology nodes.

Systematic power reduction and performance analysis of mismatch limited ADC designs

This paper focuses on several methods to save power consumption in mismatch limited ADC designs, like flash and folding architectures. Migrating existing designs to a next submicron technology helps to reduce the power consumption significantly. It is shown that decreasing bandwidth and sample rate creates a more than linear reduction of the power consumption. Both of these methods are addressed in this paper. Also the balance between power consumption of the analog and digital circuitry is examined. An existing 6-bit 1.6GS/s ADC in 0.18/spl mu/m CMOS is transferred to a 0.12/spl mu/m technology. The sampling rate is reduced to 260MS/s, the measured ERBW to 124MHz while running at only 32mW. As the bandwidth is downscaled 5/spl times/, the power consumption is reduced by 10/spl times/, which results in an improved conversion efficiency. As the design topology is unaltered, the implemented design sets a reference for evaluation of any low-power technique.

Scalable high-speed analog circuit design

The impact of scaling on the analog performance of MOS circuits was studied. The solution space for analog scaling was explored between two dimensions: a “standard digital scaling” axis and an “increased bandwidth and dynamic-range” axis. Circuit simulation was applied to explore trends in noise and linearity performance under analog operating conditions at device level and for a basic circuit block. It appears that a single scaling rule is not applicable in the analog circuit domain.

CMOS technology for mixed signal ICs

Abstract Economic and technical constraints force digital CMOS technology in a direction which is not always beneficial for analog design. The development of some analog parameters as a function of process generation is analysed. The consequences of the present developments on mixed-signal ICs are briefly discussed.