Raf Schoofs

A Design-Optimized Continuous-Time Delta–Sigma ADC for WLAN Applications

A third-order continuous-time delta-sigma (DeltaSigma) analog-to-digital converter (ADC) is presented for the conversion of an input signal bandwidth of 10 MHz. Design optimization towards minimal power consumption is demonstrated for the high-speed low-power building blocks of the DeltaSigma modulator. From this point of view, it is shown that GmC integrators are preferred over RC integrators in the low-pass filter of the modulator because they show a better tradeoff between power, speed, and accuracy. A new single-bit quantizer topology is presented that incorporates a local feedback path that improves stability using a switched-voltage technique. Finally, a design methodology for the single-bit digital-to-analog converter (DAC) in the feedback loop is proposed, focusing on the impact of high sampling rates on the stability of the converter. The presented continuous-time ADC achieves a simulated dynamic range of 72 dB and a signal-to-noise-and-distortion-ratio of 66 dB in a 10-MHz signal bandwidth. Therefore, it can be applied for WLAN broadband communication. The power consumption of the DeltaSigma modulator is limited to 7.5 mW. The chip is designed in a 0.18-mum triple-well CMOS technology

Hierarchical bottom-up analog optimization methodology validated by a delta--sigma A/D converter design for the 802.11a/b/g standard

This paper describes key points and experimental validation in the development of a bottom-up hierarchical, multi-objective evolutionary design methodology for analog blocks. The methodology is applied to a continuous-time DeltaSigma A/D converter for WLAN applications, to generate a set of Pareto-optimal design solutions. The generated performance tradeoff offers the designer access to a set of optimal design solutions, from which the designer can choose a satisfactory design point according to the performance specifications. The presented method takes advantage of the Pareto-optimal performance solutions of the hierarchical lower-level sub-blocks to generate the overall Pareto-optimal set at system level. The way the lower-level performance tradeoffs are combined and propagated to higher hierarchical levels, is one of the major key points in the bottom-up methodology. The experimental results validate the methodology for a 7-block hierarchical decomposition of a complex high-speed Delta;Sigma A/D modulator for a WLAN 802.11a/b/g standard

An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection

A hierarchical synthesis methodology for analog and mixed-signal systems is presented that fully in a novel way integrates topology selection at all levels. A hierarchical system optimizer takes multiple topologies for all the building blocks at each hierarchical abstraction level, and generates optimal topology combinations using multi-objective evolutionary optimization techniques. With the presented methodology, system-level performance trade-offs can be generated where each design point contains valuable information on how the systems performances are influenced by different combinations of lower-level building block topologies. The generated system designs can contain all kinds of topology combinations as long as critical inter-block constraints are met. Different topologies can be assigned to building blocks with the same functional behavior, leading to more optimal hybrid designs than typically obtained in manual designs. In the experimental results, three different integrator topologies are used to generate an optimal system-level exploration trade-off for a complex high-speed DeltaSigma A/D modulator

A 1 GHz continuous-time sigma-delta A/D converter in 90 nm standard CMOS

A 1 GHz continuous-time sigma-delta A/D modulator is presented. It is designed in a standard 90 nm CMOS technology. The 1-bit modulator achieves an accuracy of 10 bits in a signal bandwidth of 8 MHz. This paper focuses on the challenges the designer faces when the sampling speed increases and the supply voltage lowers. It is shown that a G m C architecture is the most power efficient filter implementation for broadband conversion. Here, the power consumption is determined by thermal noise requirements. Finally, the timing of the feedback pulse is controlled. This ensures an improved stability of the 1 GHz modulator.

A Continuous-Time Delta-Sigma Modulator for 802.11a/b/g WLAN Implemented with a Hierarchical Bottom-up Optimization Methodology

This paper presents a continuous-time delta-sigma modulator with a resolution of 10 bits in a 10 MHz signal bandwidth. It is designed in a standard 0.18 mum CMOS technology and consumes 6 mW. A hierarchical bottom-up, multi-objective evolutionary design methodology was developed to reduce design time. It takes advantage of the Pareto-optimal performance solutions of the hierarchically decomposed lower-level sub-blocks to generate the overall Pareto-optimal set at modulator level. A 7-block hierarchical decomposition of a 640-MHz DeltaSigma modulator for 802.11a/b/g WLAN applications is implemented and optimized towards power efficiency.

A GmC filter design methodology for high-speed continuous-time sigma-delta A/D converters in a deep sub-micron technology

This paper presents a design methodology for a GmC filter in a Continuous-Time (CT) Sigma-Delta A/D converter. It focuses on the challenges the designer faces when a deep sub-micron technology is used. According to the proposed methodology, a 1-bit, 3rd order CT modulator is designed. The modulator achieves an accuracy of 10 bits within a signal band of 8 MHz. The design is made in a 90 nm standard CMOS process. The small transistor dimensions enable a clock rate of 1 GHz. An analytical comparison between RC filters and GmC filters is presented based on their power consumption. It is shown that a RC filter requires an integrator loop gain-bandwidth equal to the sampling rate. This puts a severe limitation on the minimal power consumption for this type of filter. Therefore, a GmC filter implementation is chosen because it consumes the lowest power in order to meet the design specifications. Mathematical expressions for harmonic distortion and thermal noise are derived. They are interpreted in terms of a low power design approach. Since the input signal swing scales down with the supply voltage, harmonic distortion becomes less important in a deep sub-micron technology. Therefore, the thermal noise requirements determine mainly the overall power consumption of the CT modulator. Small transistor lengths enable high sampling rates, but lower the integrator output impedance. This results in a reduced DC gain of the filter. Consequently, the proposed GmC filter architecture is adjusted to provide sufficient suppression of in-band quantization noise leakage. All proposed design choices are verified by numerical simulations.

A 7.5mW, 11-bit continuous-time sigma-delta A/D converter for WLAN applications

A third-order continuous-time DeltaSigma analog-to-digital converter is designed for the conversion of an input signal bandwidth of 10MHz. Design optimization towards minimal power consumption is demonstrated for the high-speed, low-power building blocks of the modulator. The presented converter achieves a dynamic range of 72dB and a signal-to-noise-and-distortion-ratio of 66dB. The modulator consumes 7.5mW. It is integrated in a 0.18mum standard CMOS technology and occupies an area of 1.65mm2