Raghav Babulnath

Highly effective and accurate weak point monitoring method for advanced design rule (1x nm) devices

Historically when we used to manufacture semiconductor devices for 45 nm or above design rules, IC manufacturing yield was mainly determined by global random variations and therefore the chip manufacturers / manufacturing team were mainly responsible for yield improvement. With the introduction of sub-45 nm semiconductor technologies, yield started to be dominated by systematic variations, primarily centered on resolution problems, copper/low-k interconnects and CMP. These local systematic variations, which have become decisively greater than global random variations, are design-dependent [1, 2] and therefore designers now share the responsibility of increasing yield with manufacturers / manufacturing teams. A widening manufacturing gap has led to a dramatic increase in design rules that are either too restrictive or do not guarantee a litho/etch hotspot-free design. The semiconductor industry is currently limited to 193 nm scanners and no relief is expected from the equipment side to prevent / eliminate these systematic hotspots. Hence we have seen a lot of design houses coming up with innovative design products to check hotspots based on model based lithography checks to validate design manufacturability, which will also account for complex two-dimensional effects that stem from aggressive scaling of 193 nm lithography. Most of these hotspots (a.k.a., weak points) are especially seen on Back End of the Line (BEOL) process levels like Mx ADI, Mx Etch and Mx CMP. Inspecting some of these BEOL levels can be extremely challenging as there are lots of wafer noises or nuisances that can hinder an inspector’s ability to detect and monitor the defects or weak points of interest. In this work we have attempted to accurately inspect the weak points using a novel broadband plasma optical inspection approach that enhances defect signal from patterns of interest (POI) and precisely suppresses surrounding wafer noises. This new approach is a paradigm shift in wafer inspection by leveraging systematic defect locations for high sensitivity inspection, thereby enhancing the discovery and monitoring of yield-limiting defects at traditional optical inspection throughput.

Design based classification for process window defect characterization of BEOL ADI layers

As design rules shrink, lithographers incorporate complex resolution enhancement techniques (RETs) that enable lithographers to extend existing lithographic processes to print features smaller than the wavelength of light used - a process called sub-wavelength lithography. These enhancements include optical proximity correction (OPC) and phase shift mask (PSM) technology, which together reduce the size and fine-tune the shape of features on the wafer. During the photolithography patterning process, marginal RET designs can print as out-of-focus features-or not print at all, creating open circuits that translate to electrical failures within the device. Two major variables, which affect the pattern printed on the wafer, are focus and exposure (dose). A number of techniques are used today to identify the process window accurately like Focus Exposure Matrix (FEM), CD SEM1 and Process Window Qualification (PWQ). These techniques enable lithographers to understand the consequences of operating near the boundaries of the process window - allowing more informed decisions about whether to redesign the reticle or fine-tune inline defect and CD monitoring efforts to minimize the impact of the systematic defects on device yield. Particularly in back end of line (BEOL) After Develop Inspect (ADI) layers, nuisance defects (such as defects that are not visible on scanning electron microscope, defects on dummy structures, or other defects that do not affect yield) are so common, that sampling a statistically significant number of defects of interest (DOI) for PWQ becomes very time consuming and involves a lot of human effort. This paper describes the use of Design Based Classification (DBC) together with an AutoPWQ technique to improve time to results and to monitor BEOL ADI layers for process window drift. The combination of AutoPWQ + DBC method was compared to AutoPWQ alone as well as to FEM with manual sampling.

EUV stochastic defect monitoring with advanced broadband optical wafer inspection and e-beam review systems

As Extreme UltraViolet (EUV) lithography nears high volume manufacturing (HVM) adoption to enable the sub-7nm scaling roadmap, characterizing and monitoring defects that print at wafer level are of critical importance to yield. This is especially true for defects coming from the EUV mask, such as multi-layer defects, added particles or growth on mask, and for defects coming from the pattern formation process itself, also referred to as stochastic printing defects. A “Print Check” solution has been previously described.1 This technique uses full-wafer patterned optical inspection to monitor mask defects that print on the wafer. In this paper we focus on developing metrology solutions for stochastic printing defects, which are random local variations that occur between structures that should, in principle, print identically, but actually occur at significant frequencies with current state-of-the-art processes. Specifically, we discuss the importance of monitoring these defects using broadband plasma optical inspection and e-beam defect review systems. We show extensive characterizations of defects on line space patterns down to a pitch of 36nm, on contact holes at a pitch of 48nm and on logic blocks in a foundry equivalent N5 test vehicle. Analysis methods based on CD SEM and review SEM images have been described.