Raghavendra Kulkarni

A Self-Sustained CMOS Microwave Chemical Sensor Using a Frequency Synthesizer

In this paper, a CMOS on-chip sensor is presented to detect dielectric constant of organic chemicals. The dielectric constant of these chemicals is measured using the oscillation frequency shift of an LC voltage-controlled oscillator (VCO) upon the change of the tank capacitance when exposed to the liquid. To make the system self-sustained, the VCO is embedded inside a frequency synthesizer to convert the frequency shift into voltage that can be digitized using an on-chip analog-to-digital converter. The dielectric constant is then estimated using a detection procedure including the calibration of the sensor. The dielectric constants of different organic liquids have been detected in the frequency range of 7-9 GHz with an accuracy of 3.7% compared with theoretical values for sample volumes of 10-20 μL. The sensor is also applicable for binary mixture detection and estimation of the fractional volume of the constituting materials with an accuracy of 1%-2%.

A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy

A Bang-Bang Clock and Data Recovery (CDR) with adaptive loop gain strategy is presented. The proposed strategy enhances CDR jitter performance even if jitter spectrum information is limited a priori. By exploiting the inherent hard-nonlinearity of Bang-Bang Phase Detector (BBPD), the CDR loop gain is adaptively adjusted based on a posteriori jitter spectrum estimation. Maximizing advantages of analog and digital implementations, the proposed mixed-mode technique achieves PVT insensitive and power efficient loop gain adaptation for high speed applications even in limited ft technologies. A modified CML D-latch improves CDR input sensitivity and BBPD performance. A folded-cascode- based Charge Pump (CP) is proposed to minimize CP latency. The 5 G/10 G CDR prototype is fabricated in 0.18 μm CMOS technology to demonstrate the effectiveness of the proposed techniques for applications with high ratio of data-rate to ft. The proposed CDR recovers data with BER <; 2·10-13 and generates only 1.04 ps RMS and 7.5 ps peak-peak jitter. Jitter Tolerance (JTOL) test shows that the proposed CDR enhances low frequency jitter tracking and high frequency jitter filtering simultaneously for various jitter profiles. The CDR power consumption is 110.6 mW where only 3.9 mW is used for loop gain adaptation circuitry.

Estimation of porous media flow functions

Properties important for describing the flow of multiple fluid phases through porous media are represented as functions of state variables (fluid saturations). A generalized procedure is presented to obtain the most accurate estimates of the multiphase flow functions from the available experimental data. The procedure is demonstrated for several different experimental designs, including a novel experiment in which fluid saturations are measured using nuclear magnetic resonance imaging. A method to evaluate the accuracy of the estimates is presented, and its use for assessing experimental design is demonstrated.

UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations

An integrated ultrahigh-frequency (UHF) receiver is presented. A systematic analysis to quantify the interdependence of baseband filter and analog-to-digital converter (ADC) dynamic range in broadband receivers is presented. This analysis shows that: (1) low-order Butterworth filters are favorable when undesired power is dominated by far out blockers and (2) high-order inverse Chebyshev filters can reduce the resolution of a subsequent ADC by up to two additional bits in the presence of adjacent analog narrowband blockers. Based on the analysis, a cascaded, programmable, hybrid active-RC and switched-capacitor (SC) baseband filter is proposed. An all-digital nonoverlap clock tuning system to minimize the variation of available settling time window in SC circuits is also proposed. The receiver integrates the proposed filter with an RF variable gain amplifier (RFVGA) and a passive mixer. This receiver achieves a measured noise figure of 7.9 dB, an IIP3 of -8 dBm at maximum gain and +2 dBm at 9-dB RF attenuation. The chip consumes 120 mW (RFVGA, mixer and I-channel baseband) from 1.8-V analog/2.5-V digital dual supply and occupies 2.14 mm2 in IBM 0.18-μm RF CMOS technology.

Voltage mode driver for low power transmission of high speed serial AER Links

This paper presents a voltage-mode high speed driver to transmit serial AER data in scalable multi-chip AER systems. To take advantage of the asynchronous nature of AER (Address Event Representation) streams, this implementation allows an energy efficient burst-mode operation. This is achieved by switching on/off the driver in data pauses to reduce static power consumption. Impedance matching is calibrated continuously to track temperature variations, obtaining an optimal performance without degrading the data rate. Power management techniques for switching drivers are discussed and an internally compensated high speed regulator is presented. The system has been designed in a 0.35µm CMOS technology to transmit data rates up to 500Mbps using Manchester enconding. Layout extracted simulation results are presented, which include all interconnect parasitics. Estimated peak rate is 15Meps for 32 bit events. Simulated power consumption of transmitter and receiver at peak rate is 33.2mW, while below 100 Keps is 1.3mW.

A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings

This paper presents a low power fast ON/OFF switchable voltage mode implementation of a driver/receiver pair intended to be used in high speed bit-serial Low Voltage Differential Signaling (LVDS) Address Event Representation (AER) chip grids, where short (like 32-bit) sparse data packages are transmitted. Voltage-Mode drivers require intrinsically half the power of their Current-Mode counterparts and do not require Common-Mode Voltage Control. However, for fast ON/OFF switching a special high-speed voltage regulator is required which needs to be kept ON during data pauses, and hence its power consumption must be minimized, resulting in tight design constraints. A proof-of-concept chip test prototype has been designed and fabricated in low-cost standard 0.35 μm CMOS. At ±500 mV voltage swing with 500 Mbps serial bit rate and 32 bit events, current consumption scales from 15.9 mA (7.7 mA for the driver and 8.2 mA for the receiver) at 10 Mevent/s rate to 406 μA ( 343 μA for the driver and 62.5 μA for the receiver) for an event rate below 10 Kevent/s, therefore achieving a rate dependent power saving of up to 40 times, while keeping switching times at 1.5 ns. Maximum achievable event rate was 13.7 Meps at 638 Mbps serial bit rate. Additionally, differential voltage swing is tunable, thus allowing further power reductions.

Design of Two-Phase Displacement Experiments

This paper presents and demonstrates a systematic approach to the selection of experimental designs leading to accurate estimates of relative permeability and capillary pressure functions for two-phase flow in porous media. The objective is to select the most appropriate experimental designs for determining the flow functions accurately within the saturation range covered by the experimental data. The work is based on a linearized covariance analysis. In this analysis we utilize analytical sensitivity coefficients to calculate confidence intervals for the flow functions. These confidence intervals are estimates of the accuracy with which the flow functions can be determined for a given experimental design. We validate the confidence interval estimates through a Monte Carlo study. A previously reported non-linearity measure seems not to be applicable for determining the utility of the linearized covariance analysis for the porous media fluid flow model.

A broadband 470–862 MHz direct conversion CMOS receiver

This work presents an integrated ultra high frequency (UHF), broadband direct-conversion receiver. The receiver integrates a single-ended RFVGA, an on-chip single-to-differential balun, a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. Targeted to operate between 470–862 MHz, the receiver achieves a noise figure of 7.9dB, an IIP3 of −8dBm at maximum gain and an IIP3 of +2dBm at 9dB RF attenuation. The gain- and frequency-programmable baseband section implements an 8th order inverse chebyshev low pass approximation achieving >42dB attenuation at an offset of 1.75 MHz for the 4 MHz frequency setting. Overall, the receiver consumes 120mW from 1.8V analog/2.5V digital dual supply and occupies 2.14mm2 in IBM 0.18/im RFCMOS technology.

An 802.11a/b/g/n/ac WLAN Transceiver for 2×2 MIMO and simultaneous dual-band operation with +29 dBm Psat integrated power amplifiers

This paper describes the first dual-band MIMO 802.11a/b/g/n/ac WLAN RF transceiver capable of simultaneous dual-band operation. The measured receiver sensitivity of 2 GHz at 54 Mbps is -78.3 dBm and of 5 GHz for VHT80 is -66 dBm. The 802.11ac 2×2 MIMO 20 MHz MCS0 2 GHz and 5 GHz receiver sensitivity levels are -96 dBm and -95.5 dBm respectively. Integrated power amplifiers with Psat of +29 dBm enable the 2 GHz transmitters to achieve TX output power of +23.5 dBm at 54 Mbps 64-QAM. The 5 GHz transmitters achieve +17 dBm output for VHT80 256-QAM. This WLAN-BT connectivity SoC is implemented in 40 nm CMOS technology.

Analog Baseband Filter Design Considerations for Wireless Receivers

Design considerations applicable to analog baseband design for wireless receivers are discussed. Importance of out-of-band linearity and blocker tolerance requirements in analog filters is highlighted. A systematic analysis to evaluate the interdependence of analog baseband filter and a subsequent analog-to-digital converter (ADC) performance is presented. The analysis quantifies the effect of digital and analog modulated blockers on the design of the baseband filter specifications (order and approximation) and the ADC dynamic range. A cascaded, programmable, hybrid active-RC and switched capacitor low-pass filter suitable for a broadband UHF wireless receiver is illustrated as an example. Experimental results from the baseband filter and the prototype receiver are also included.