Rainer Pelzer

New Results on Plasma Activated Bonding of Imprinted Polymer Features for Bio MEMS Applications

Nanoimprint Lithography is a well-acknowledged low cost, high resolution, large area 3D patterning process for polymers. It includes the most promising methods: high pressure hot embossing (HE) and UV-Nanoimprint Lithography (UV-NIL). Curing of the imprinted structures is either done by cooling down below the glass transition temperature of the thermoplastic polymer in case of HE or by subsequent UV-light exposure and cross-linking in case of UV-NIL. Both techniques allow rapid prototyping for high volume production of fully patterned substrates for a wide range of materials. The advantages of using polymer substrates over common Micro-Electro-Mechanical Systems (MEMS) processing materials like glass, silicon or quartz are: bio-compatible surfaces, easy manufacturability, low cost for high volume production, suitable for use in micro- and nano-fabrication, low conductivity, wide range of optical properties just to name a few. We will present experimental results on HE processes with PMMA as well as UV-NIL imprints in selected UV-curable resists. In the second part of the work we will describe the bonding techniques for packaging of the micro or nano structures. Packaging of the imprinted features is a key technology for a wide variety of field of applications: µ-TAS, biochemistry, micro-mixers, micro-reactors, electrophoresis cells, life science, micro-optical and nano-optical applications (switches) nanofluidics, data storage, etc. for features down to sub-100 nm range. Most bonding techniques for polymer use adhesives as intermediate layers. We will demonstrate a promising technique for dense and very strong bonds using plasma activation of polymers and glass. This bonding technology allows for bonding at low temperatures well below the glass transition temperature of the polymers, which will ensure that the structures are not deformed.

Wafer-to-Wafer Bonding Techniques: From MEMS Packaging to IC Integration Applications

Device stacking and packaging on wafer-level plays a key role for the continuous miniaturization, expansion of functionality and reduction of production costs of MEMS and MCMs. The field of applications for integrated devices and MEMS is huge and the packaging requirements for the different systems are versatile. Driven by the automotive industry, extensive research and development in the field of wafer bonding resulted in a variety of different technologies. The primary targets of packaging steps are not only protecting devices from environmental influences, it is also important to compensate for stress, or to enable final testing in an efficient manner. The type of interaction of the MEMS with the environment determines the design, packaging materials and the packaging technique. Inappropriate choice of the package may result in poor reliability and narrow the spectrum of the systems applications. Therefore its not surprising that packaging represents the major part of the cost of the whole MEMS device (30-50% of the costs may represent packaging; for some devices up to 80% have been reported). As several of these techniques are suitable for 3D stacking of IC chips as well, we will explain and discuss these requirements for this application, too

Nanoimprint lithography: full wafer replication of nanometer features

Nanoimprint Lithography (NIL) is a fast, high resolution replication technology for micromechanics, microbiology and even for microelectronic applications in the sub-100nm range. The technique has been demonstrated to be a very promising next generation technique for large-area structure replication up to wafer-level in the micrometer and nanometer scale. For producing nanometer structures the capital investments required are much lower compared to other next generation methods (e-beam writing, x-ray lithography, EUV lithography, ...). Nanoimprint Lithography is based on two different techniques: Hot Embossing (HE) and UV-Nanoimprint Lithography (UV-NIL). Both methods can be used for replicating dense and isolated features in the range of 70nm to 100μm simultaneously on up to 200mm wafers.

Advanced low temperature bonding technologies

The different fields and especially its various applications for microelectromechanical systems (MEMS) prevent the use of uniform packaging techniques for all types of /spl mu/-device. Several bonding techniques performed at wafer-scale, with the advantage of protecting the device against particles, contaminations or even damage during the sawing and dicing process are used right now. Most of these techniques are performed at high temperatures during the bond, wet cleaning process steps - totally inapplicable for /spl mu/-moving parts - or insufficient hermeticity in the final package. Bonding techniques based on dry plasma activation and adhesive wafer-level bonding of MEMS are therefore a very interesting alternative to the common techniques. Main advantages of these two techniques are: temperature sensitive devices or heterogeneous materials with different CTE can be bonded together on wafer scale; there is no wet activation or cleaning processes involved.

Nanostructuring of polymers by Hot Embossing Lithography

While researchers of ever more advanced NGL systems are still struggling to demonstrate the feasibility to manufacture features well below 100 nm at an affordable cost and a reasonable throughput, nanoimprint technologies are emerging as a possible answer to these challenges. 100 nm patterns are imprinted with a fully patterned 4 inch diameter stamp in a low-temperature embossing process. In low temperature imprinting processes with polymers having very low glass transition temperatures heating and cooling cycles are minimized. This enables to increase the throughput of a hot embossing process, which is important for potential industrial applications.

Advances in lithography technologies for wafer-level packaging

With the continuous reduction in IC feature size, the increased demand for higher speed and lower power consumption and with the simultaneous increase of I/O, wafer-level packaging is today an interesting solution for IC and micro electro mechanical systems(MEMS) packaging having as result the cost decrease and increased performance. With wafer-level packaging (WLP) the die and the package are fabricated and tested on the wafer prior to the dicing. Among the advantages of WLP are smaller IC package and a significant of-scale cost reduction due to high throughput of the parallel running packaging and electrical testing steps on wafer size. Thick resist-coating, lithography and wafer-to-wafer alignment for subsequent bonding are key enabling technologies for WLP. The roadmap for transistor scaling predicts further increase of circuit complexity, which comes along with higher pin count densities (pins per unit area) and therefore smaller feature sizes. This fact makes specialized and unique processing equipment development a must. This paper is summarizing the specific process requirements and will review the current technologies supporting WLP.

Optical module fabrication using nanoimprint technology

UV-NanoImprint Lithography (NIL) is a fast and low cost method, which becomes an increasingly important instrument for fabrication of μ-TAS and telecommunication devices. The key elements of UV-NIL are transparent molds and low viscosity resists. Two different transparent mold materials, allowing UV curing through the stamp, were developed: rigid quartz or flexible PDMS. Typical resist viscosities are in a range of <100mPas, ensuring fast and successful filling of the stamp cavities. UV-curing is carried out at a wavelength of 350-450 nm.

Thick Film Lithography Techniques utilizing state-of-the-art Proximity Aligners for BEoL Applications

Wafer-level packaging is a promising technology to meet future demands of increased performance for advanced integrated circuits with tighter pitch and higher I/O counts (higher feature density). Innovative equipment technology for new full field lithography techniques is at the forefront of the technology roadmap and perfectly suited for wafer-level packaging, including bond-bad redistribution and fine pitch wafer bumping applications. Typically advanced packaging applications involve thick resist processing of films in the range of up to 100mum, exposure of conformal films on topography and the requirement for steep, controllable sidewall angles. The smallest required resolutions are in the range of 20mum in thick film photoresists for bumping applications and 3-5mum for pad redistribution lines in dielectric resins, like BCB. The alignment and exposure requirements for the lithographic process in WLP will be discussed. Projection aligners are still the first choice for WLP, even if the investments are much higher compared to the 1times proximity aligner. We will demonstrate that state-of-the-art proximity aligner fulfil all requirements for WLP and embedded passives

μ-Device fabrication and packaging below 300°C utilizing plasma-assisted wafer-to-wafer bonding

Wafer-to-wafer bonding techniques, such as anodic bonding or high temperature silicon direct fusion bonding, have been in development since the late 1960s and became key technologies for MEMS manufacturing. Plasma assisted wafer bonding is an emerging method offering several advantages over traditional bonding techniques. This technology was first discovered and patented in the early 1990s and has been used in SOI production for the past five years. Now plasma activation benefits are being used to enable 3D integration and advanced MEMS device fabrication and packaging. The main advantage of plasma assisted bonding is that high strength direct bonds between substrates, like Si, glass or polymers, can be achieved already below 300°C.