Viorel Dragoi

Plasma activated wafer bonding : The new low temperature tool for mems fabrication

Manufacturing and integration of MEMS devices by wafer bonding often lead to problems generated by thermal properties of materials. These include alignment shifts, substrate warping and thin film stress. By limiting the thermal processing temperatures, thermal expansion differences between materials can be minimized in order to achieve stress-free, aligned substrates without warpage. Achieving wafer level bonding at low temperature employs a little magic and requires new technology development. The cornerstone of low temperature bonding is plasma activation. The plasma is chosen to compliment existing interface conditions and can result in conductive or insulating interfaces. A wide range of materials including semiconductors, glasses, quartz and even plastics respond favorably to plasma activated bonding. The annealing temperatures required to create permanent bonds are typically ranging from room temperature to 400°C for process times ranging from 15-30 minutes and up to 2-3 hours. This new technique enables integration of various materials combinations coming from separate production lines.

Cyclo-olefin polymer direct bonding using low temperature plasma activation bonding

Low temperature direct bonding method of Cyclo-Olefin Polymer (COP) plates (20mm /spl times/ 40mm /spl times/ 2.0mm) has been developed employing surface plasma treatment with various gases such as N/sub 2/, O/sub 2/, and 10%-H/sub 2//Ar. Surface energy of the bonded interface has been measured by razor blade method. Reasonable bonding strength for flow devices was achieved even at room temperature. The contact angle measurement on the sample surfaces after plasma exposure indicated that the plasma activated surfaces became hydrophilic and this activated state lasted for longer than 2 months. This method is useful to fabricate micro-flow devices for single-molecule level optical bio-detection systems that requires less residual stress and deformation after bonding.

3D interconnect through aligned wafer level bonding

Wafer level packaging and 3D interconnect technologies are driven by increasing device density and functionality as well as reduction of total packaging cost. Key enabling technologies for 3D interconnect are high precision alignment and bonding systems and thick resist processing. A unique processing equipment has been developed to meet high volume production requirements. This paper reviews advances in equipment processing capabilities and provides a guideline for new processing techniques available. Wafer to wafer alignment can be carried out in various ways. Traditionally aligned wafer bonding is a well-established technology in the MEMS industry. Special requirements for 3D interconnects are high accuracy, the use of single side processed wafers and 8 inch capability. A comparison of wafer alignment technologies is presented. Also, a novel face-to-face alignment method is described and analyzed in terms of alignment accuracy before and after bonding. Wafer bonding is carried out subsequent to the alignment step in a separate process module. A summary of different bonding methods is given. Intermediate layers that act as bonding agent can be spun on to the wafer. Such coating processes for wafer level packaging applications vary greatly from the requirements for VLSI processing. VLSI photoresist processes use thin layers to transfer small features with sub-micron tolerances. Wafer level bumping typically is performed with 5-150 /spl mu/m films, to transfer large (20-250 /spl mu/m) features, with tolerances approaching micron scale. HDI applications require thicker adhesive layers. The paper concludes with application examples with different intermediate layers such as BCB.

CMOS image sensor wafer-level packaging

This article presents the advances in wafer-level processing and integration techniques for CMOS image sensor module manufacturing. CMOS image sensors gave birth to the low-cost, high-volume camera phone market and are being adopted for various high-end applications. The backside illumination technique has significant advantages over the front-side illumination due to separation of the optical path from the metal interconnects. Wafer bonding plays a key role in manufacturing backside illuminated sensors. The cost-effective integration of miniaturized cameras in various handheld devices becomes realized through the introduction of CMOS image sensor modules or camera modules manufactured with wafer-level processing and integration techniques. We developed various technologies enabling wafer-level processing and integration, such as (a) wafer-to-wafer permanent bonding with oxide or polymer layers for manufacturing backside illuminated sensor wafers, (b) wafer-level lens molding and stacking based on UV imprint lithography for making wafer-level optics, (c) conformal coating of various photoresists within high aspect ratio through-silicon vias, and (d) advanced backside lithography for various metallization processes in wafer-level packaging. Those techniques pave the way to the future growth of the digital imaging industry by improving the electrical and optical aspects of devices as well as the module manufacturability.

Metal Thermocompression Wafer Bonding for 3D Integration and MEMS Applications

Due to the diffusion mechanism one of the most important aspects for the bonding process is to control the surface status. Contamination or native oxides may impact consistently on the process result (defect-free, high bond strength and particularly for 3D applications low resistivity). Metal oxides have different behavior and have to be treated accordingly. For example in case of Copper two different approaches are used in order to minimize the oxide-induced issues: metal surface protection with an organic layer (e.g. Benzotriazole) and oxide removal by wet etching or by heated gas treatment (e.g. forming gas). If this method works in case of Copper it doesn’t make it a general rule: in case of Aluminum, the native oxide is chemically very stable and can not be removed as in case of Copper. In such case other methods are employed (e.g. mechanical breakage of oxide).

Plasma Activated Wafer Bonding of Silicon: In Situ and Ex Situ Processes

Plasma activated wafer bonding generated a high interest in last decade due to the important process temperature reduction. With the main advantage of bringing some applications at industrial degree of feasibility. An example of process which benefits from this new process is silicon fusion bonding: by using plasma activation the bond process temperature and time are reduced at values which make wafer bonding compatible with industrial manufacturing requirements. A newly developed process allowing bonding of two substrates in the plasma activation chamber is foreseen as a very interesting approach for numerous applications, especially in the field of engineered substrates fabrication.

Wafer bonding with metal layers for MEMS applications

Metal films can be used as bonding layers at wafer-level in MEMS manufacturing processes for device assembly as well as just for electrical integration of different components. One has to distinguish between two categories of processes: metal thermo-compression bonding on one side, and bonding with formation of an eutectic alloy layer or an intermetallic compound. The different process principles determine also the applications area for each. From electrical interconnections to wafer-level packaging (with special emphasis on vacuum packaging) metal wafer bonding is a very important technology in MEMS manufacturing processes.

Reversible wafer bonding for reliable compound semiconductor processing

Reversible wafer bonding is a process enabling reliable compound semiconductor wafer handling for multi-step processes including photolithography, thinning, etching or coating. Two processes using wax and dry film adhesives are presented in this paper.

Cu-Cu wafer bonding: An enabling technology for three-dimensional integration

Wafer-level hybrid bonding with Cu/SiO2 is a very promising technique to fabricate three-dimensional integrated circuits, because it enables high performance operation with low power consumption as well as low 3D stacking costs. For a successful hybrid bonding process, the particular bonding properties of unstructured Cu-Cu and Si-SiO2 wafer bonding were investigated. For Cu-Cu bonding, the Cu oxide removal prior to bonding is one of the keys to success. The combination of ex-situ citric acid and in-situ forming gas pre-treatments before bonding resulted in sufficient bonding quality at low temperature as low as 200°C. In the case of plasma activated Si-direct wafer bonding, a bonding strength similar to the Si bulk fracture strength was achieved. So far, the isolated Si-direct and Cu-Cu thermo-compression wafer bonding processes were successfully demonstrated. Finally, crucial interdependencies, such as the plasma activation on Cu surfaces and the citric acid treatment on Si surfaces, for a successfully hybrid wafer bonding were presented.

CMOS wafer bonding for back-side illuminated image sensors fabrication

Backside illuminated CMOS image sensors were developed in order to encompass the pixel area limitation due to metal interconnects. In this technology the fully processed CMOS wafer is bonded to a blank carrier wafer and then back-thinned in order to open the photosensitive sensor area. The process flows of the two main competing wafer bonding technologies used for this manufacturing process (adhesive bonding and low temperature plasma activated direct wafer bonding with polymer layers) will be reviewed.