Paul Kettner

Temporary Bonding and DeBonding Enabling TSV Formation and 3D Integration for Ultra-thin Wafers

As the microelectronics industry promotes emerging and future applications, new and improved methods will be necessary to meet the manufacturing challenges associated with new products and processes. Emerging products and applications such as heterogeneous integrated chips (3D, TSV-through silicon via), radio-frequency identification tags, ever denser memory devices along with the advent of new advanced packaging technologies for a variety of products ranging from logic to memory to image sensors (CIS) require increasingly thinner substrates. While thin (<100 mum) silicon wafers exhibit increased flexibility, which in some cases is actually desired, such wafers also exhibit increased instability and fragility. The increased degree of fragility becomes even more pronounced in compound semiconductor wafers because of the mechanical properties of the constituent materials. The lack of mechanical stability and the increased fragility present a major challenge to maintaining high yield levels in volume manufacturing environments. A reliable support and handling solution is needed to overcome the above-mentioned challenges while maintaining yield levels compatible with low-cost, high-yield manufacturing processes. The solution of choice must enable safe, reliable handling of the substrates through back-thinning and backside processing while being compatible with existing (already installed) equipment lines and manufacturing processes. The most promising and most widely investigated handling solution for UltraThinreg wafers is the use of temporary bonding and debonding techniques utilizing a rigid carrier wafer to provide sufficient mechanical support. Once the product wafer is temporarily bonded to the carrier wafer, it is ready for backside processing including back-thinning, through-silicon via formation, etc. The product wafers can either be pre-processed wafers with CMOS devices as well as e.g. substrates with high-topographies like solder-balls. After completion of the backside processing steps, the product wafer can be released from the carrier wafer and proceed to final packaging processes. This paper will discuss and describe the temporary bonding process step technology, including spin/spray coating process to apply the high performance BrewerScience intermediate adhesive and the subsequent bonding step in detail. The EVG850TB (temporary bonding) equipment and the related process modules to cover this process are explained in addition. Furthermore, backside-processes (like e.g. thinning, backside metallization,.etc) which are typically applied after bonding to form e.g. TSV (through silicon vias) and the corresponding process performance are described. Once the original bonded waferstack went successfully through the backside process steps, debonding will be performed. DeBonding, in this case means, that first the thin wafer is getting debonded via thermally activated slide lift-off approach from the carrier wafer, cleaned in a single wafer cleaning chamber in order to remove the remaining adhesive residuals and than transferred to the dedicated output format. Output formats typically are either filmframe carriers, dedicated wafer cassettes, coin stack packing canisters or e.g. single wafer carriers. The carrier wafer is also getting cleaned and can then be reused again immediately for another bond-process. The EVG850DB (debonding bonding) equipment and the related process modules to cover this process are explained in detail. The paper will conclude with a discussion and comparison of silicon and glass carriers used for temporary bonding with respect to process integration and CoO.

New Results on Plasma Activated Bonding of Imprinted Polymer Features for Bio MEMS Applications

Nanoimprint Lithography is a well-acknowledged low cost, high resolution, large area 3D patterning process for polymers. It includes the most promising methods: high pressure hot embossing (HE) and UV-Nanoimprint Lithography (UV-NIL). Curing of the imprinted structures is either done by cooling down below the glass transition temperature of the thermoplastic polymer in case of HE or by subsequent UV-light exposure and cross-linking in case of UV-NIL. Both techniques allow rapid prototyping for high volume production of fully patterned substrates for a wide range of materials. The advantages of using polymer substrates over common Micro-Electro-Mechanical Systems (MEMS) processing materials like glass, silicon or quartz are: bio-compatible surfaces, easy manufacturability, low cost for high volume production, suitable for use in micro- and nano-fabrication, low conductivity, wide range of optical properties just to name a few. We will present experimental results on HE processes with PMMA as well as UV-NIL imprints in selected UV-curable resists. In the second part of the work we will describe the bonding techniques for packaging of the micro or nano structures. Packaging of the imprinted features is a key technology for a wide variety of field of applications: µ-TAS, biochemistry, micro-mixers, micro-reactors, electrophoresis cells, life science, micro-optical and nano-optical applications (switches) nanofluidics, data storage, etc. for features down to sub-100 nm range. Most bonding techniques for polymer use adhesives as intermediate layers. We will demonstrate a promising technique for dense and very strong bonds using plasma activation of polymers and glass. This bonding technology allows for bonding at low temperatures well below the glass transition temperature of the polymers, which will ensure that the structures are not deformed.

New technologies for advanced high density 3D packaging by using TSV process

There is no question that 3D integration will be the next generation of packaging. This requires new technologies from ultra thin wafer handling to wafer to wafer bonding with 3D inter substrate connections. TSV is a process in which wafers are thinned, stacked and interconnected to significantly improve electrical performance such as signal transmission, interconnect density, reduced power consumption, form factor and manufacturing costs.

Wafer-to-Wafer Bonding Techniques: From MEMS Packaging to IC Integration Applications

Device stacking and packaging on wafer-level plays a key role for the continuous miniaturization, expansion of functionality and reduction of production costs of MEMS and MCMs. The field of applications for integrated devices and MEMS is huge and the packaging requirements for the different systems are versatile. Driven by the automotive industry, extensive research and development in the field of wafer bonding resulted in a variety of different technologies. The primary targets of packaging steps are not only protecting devices from environmental influences, it is also important to compensate for stress, or to enable final testing in an efficient manner. The type of interaction of the MEMS with the environment determines the design, packaging materials and the packaging technique. Inappropriate choice of the package may result in poor reliability and narrow the spectrum of the systems applications. Therefore its not surprising that packaging represents the major part of the cost of the whole MEMS device (30-50% of the costs may represent packaging; for some devices up to 80% have been reported). As several of these techniques are suitable for 3D stacking of IC chips as well, we will explain and discuss these requirements for this application, too

Thin wafer handling and processing-results achieved and upcoming tasks in the field of 3D and TSV

As microelectronic applications and technologies are getting more demanding, it is being demonstrated that the 3rd (vertical) dimension on wafer-processing technology is enabling applications and products with higher performance. Approaching the 3rd dimension in wafers is actually considered and realized through emerging TSV (through silicon via) technology and thinned wafers at the same time. Thin (<100 ¿m) silicon wafers which are commonly used for TSV formation exhibit increased instability and fragility. The lack of mechanical stability and the increased fragility present a major challenge to maintain high yield levels in volume manufacturing environments. The most accepted handling solution for UltraThin® wafers is the use of temporary bonding and debonding techniques utilizing a rigid carrier wafer to provide sufficient mechanical support. Once the product wafer is temporarily bonded to the carrier wafer, it is ready for backside processing including back-thinning, through-silicon via (TSV) formation, etc. The product wafers can be pre-processed wafers with CMOS devices as well as e.g. substrates with high-topographies like solder-balls. Additional stacking of ultra thin wafers or bonding chips to thin wafers are new requirements to be considered.

Thin wafer processing - yield enhancement through integrated metrology

Thin wafer handling and processing is performed by temporary bonding to a rigid carrier wafer. The rigid carrier wafer gives mechanical support during wafer thinning and backside processing. Finally the thin wafer is debonded from the carrier wafer and attached to a dicing tape on film frame. While this technology has been demonstrated for a couple of years now in pilot line and small volume, it is an entirely different story to transfer such a technology to high volume manufacturing (HVM).

Nanoimprint lithography: full wafer replication of nanometer features

Nanoimprint Lithography (NIL) is a fast, high resolution replication technology for micromechanics, microbiology and even for microelectronic applications in the sub-100nm range. The technique has been demonstrated to be a very promising next generation technique for large-area structure replication up to wafer-level in the micrometer and nanometer scale. For producing nanometer structures the capital investments required are much lower compared to other next generation methods (e-beam writing, x-ray lithography, EUV lithography, ...). Nanoimprint Lithography is based on two different techniques: Hot Embossing (HE) and UV-Nanoimprint Lithography (UV-NIL). Both methods can be used for replicating dense and isolated features in the range of 70nm to 100μm simultaneously on up to 200mm wafers.

Comparison of Enabling Wafer Bonding Techniques for TSV Integration

In this study are compared the technical merits and demerits of three bonding methods suitable for manufacturing 3D-ICs. Patterned metal thermo-compression bonding facilitates fine-pitch, high-density TSV stacking with lower electrical resistance and higher mechanical strength. Direct Cu-Cu bonding is preferred over transient liquid phase bonding with Sn or Sn alloys, but reliable Cu-Cu bonds result only from high process temperature and long process time. Both bonding temperature and post-bond annealing temperature have the most significant influence on Cu-Cu bond properties. The pre-bonding of silicon oxide bonds occurs at room temperature and thus does not induce any run-out errors in wafer alignment, resulting in higher post-bond alignment accuracy. Subsequent heating to high temperatures is necessary to achieve covalent bonds, but modifying the surface chemistry by plasma activation allows the formation of strong chemical bonds at significantly lower annealing temperatures (200–400°C). Adhesive bonding has such advantages as low bonding temperature and process time compared to metal bonding, the tolerance to wafer topography and surface conditions, and the ability to join any wafer materials. However, the material reflow imposes some challenges for maintaining the alignment accuracy and another major concern is the reliability of polymer adhesives during the post-bond processes.Copyright

Advanced low temperature bonding technologies

The different fields and especially its various applications for microelectromechanical systems (MEMS) prevent the use of uniform packaging techniques for all types of /spl mu/-device. Several bonding techniques performed at wafer-scale, with the advantage of protecting the device against particles, contaminations or even damage during the sawing and dicing process are used right now. Most of these techniques are performed at high temperatures during the bond, wet cleaning process steps - totally inapplicable for /spl mu/-moving parts - or insufficient hermeticity in the final package. Bonding techniques based on dry plasma activation and adhesive wafer-level bonding of MEMS are therefore a very interesting alternative to the common techniques. Main advantages of these two techniques are: temperature sensitive devices or heterogeneous materials with different CTE can be bonded together on wafer scale; there is no wet activation or cleaning processes involved.

Low temperature packaging of BioMEMS and Lab-on-chip devices

BioMEMS in general and specifically Lab-on-chip devices for point-of-care diagnostics offer tremendous potential to improve the health care situation in developed and developing countries. Lab-on-chip devices enable the widespread and fast detection of infectious diseases as well as the continuous diagnosis and customized treatment of chronic diseases like diabetes. Implementing microfluidics and micromanufacturing enables massive parallelization of the diagnosis thereby allowing multiple different tests at once.