Raj Navinchandra Master

Ceramic mini-ball grid array package for high speed device

We have developed a Ceramic Mini Ball Grid Array (BGA) package for a high speed switch chip (200 MHz) application. In this paper, we describe the 0.5 mm pitch mini BGA package and the processes developed to fabricate this package. In addition, a matching ceramic socket that was developed to test the high speed switch chips is also briefly reviewed. The mini-BGA process enabled the packaging of the switch chip in a 21 mm ceramic substrate with 1521 solder ball connections. The main difference between the mini solder ball connections described here and conventional ceramic ball grid array (CBGA) packages is that 60/40 Pb/Sn eutectic solder is used in the mini-BGA package compared to 90/10 Pb/Sn solder balls used in CBGA packages.

Ceramic column grid array for flip chip applications

Ceramic Column Grid Array (CCGA) technology was introduced by IBM several years ago. The purpose of the Column Grid Array (CGA) technology was its improved reliability compared to the Ball Grid Array due to height and compliance. This paper describes several process improvements in fabricating the columns onto the substrates. These improvements include attaching the columns to the ceramic substrate using no clean flux and the ability to rework cast columns during the fabrication of the module. In addition, stress testing was completed to validate the use of the Coffin-Manson equation in predicting the fatigue life as a function of column length, as well as a bridge between two accelerated thermal cycling (ATC) conditions, 0-100/spl deg/C and -55-125/spl deg/C.

Flip-chip interconnection technology for advanced thermal conduction modules

Area array solder bumps on silicon devices, known as C4 balls, have been successfully used in terminating logic and memory devices to ceramic substrates in numerous IBM products over two decades. With the IBM System 390/ES9000 series of mainframe computers, this highly reliable chip termination technology has achieved improved interconnection density and total number of chip I/O connections per module. In addition, in the models 820 and 900 of ES9000 series, a novel materials set, namely glass-ceramic with Cu internal metallization along with thin-film redistribution wiring on top, has been introduced for multilayered ceramic substrates. Key elements of advanced glass-ceramic substrate technology relevant to flip-chip joining are reviewed. This is followed by a discussion of device join and replace processes used in advanced thermal conduction modules which also have decoupling capacitors which are attached by C4 solder reflow. Optimization of the top surface metallurgy and device join parameters necessary to achieve reliable joining of more than 70000 solder balls per module is discussed.<<ETX>>

Device interconnection technology for advanced thermal conduction modules

The use of area array solder bumps on silicon devices known as controlled collapse chip connection (C4) balls for terminating logic and memory devices to ceramic substrates has been extended in both interconnection density and total number of chip I/O connections per module. In addition, a novel materials set, namely glass-ceramic with copper internal metallization along with thin film redistribution wiring on the top surface, has been introduced for multilayered ceramic substrates. Key elements of advanced glass-ceramic substrate technology relevant to flip-chip joining are reviewed. This is followed by a discussion of device join and replace processes used in advanced thermal conduction modules (ATCMs). These models have decoupling capacitors which are attached by C4 solder reflow. Optimization of the top surface metallurgy and device join parameters necessary to achieve reliable joining of more than 70,000 solder balls per module is discussed. >

Cosintering process for glass-ceramic/copper multilayer ceramic substrate

In order to improve the electrical performance of the substrate for 3081 mainframe computers, a new material system consisting of glass-ceramic and copper metallurgy was developed for the system 390/ES9000 computers. The glass-ceramic package for the system 390/ES9000 is made up of 63 layers of green sheets screened with copper thick film paste and laminated under pressure to form a green body. The authors describe the challenges and solutions in cosintering the glass-ceramic and copper to form a dense package with the desired mechanical and electrical properties. A steam sintering process that is based on sound theoretical principles has been developed. This process has allowed packaging of a low dielectric constant ceramic with a high conductivity copper conductor. >

A low cost MCM-D process for flip chip and wirebonding applications

Multi-chip modules using deposited dielectric materials (MCM-D) have been produced at IBM Microelectronics Packaging Facility for over a decade. To take full advantage of this package, IBM uses flip chip technology to minimize the required substrate and silicon active area. The terminal or bonding metals for chip to substrate interconnection have been deposited by a variety of methods including electroplating and electroless plating combinations, and recently, stencil lift-off (L/O) of evaporated film. Here, the Cr/Cu/Ni/Au metallurgy was deposited not only on the interconnecting pad areas, but also on the redistribution lines. A selective deposition process was developed to eliminate the metal on the lines. Two terminal metallurgies were evaluated by this selective process, namely Cr/Cu/Ni/Au and Cr/Cu/Co/Au. This paper will cover interconnection aspects with respect to material/solder interaction of the IBM Controlled Collapse Chip Connection (C4) process with 97 Pb/3 Sn solder and wire bonding as practiced on terminal metal pads fabricated by a selective deposition process. Reliability evaluation of this new process and Co metallurgy will also be discussed.

Material considerations for multilayer ceramic capacitors

The role of material properties in the fabrication of multilayer ceramic structures is examined with emphasis on the shrinkage behavior of both the ceramic and the metallurgy used in the fabrication of the multilayer ceramic capacitors. A typical ceramic material used is barium titanate, and the typical electrode used is made of palladium. Shrinkage behavior is key to the mechanical integrity of the multilayer ceramic capacitors. The author discusses the effect of physical parameters such as particle size, shape, and surface area, as well as the effect of processing parameters. Some methods of altering the shrinkage behavior are also described. It is shown that an important consideration in the case of palladium electrodes made of fine palladium powders is the oxidation of palladium in air and the accompanying volume change.<<ETX>>