Rajakrishnan Radjassamy

Faster power estimation of CMOS designs using vector compaction - a fractal approach

Low power digital complementary metal oxide semiconductor (CMOS) circuit design requires accurate power estimation. In this paper, we present a compaction algorithm for generating compact vector sets to estimate power efficiently. Power can be estimated using dynamic (simulation) or static (statistical/probabilistic) techniques. Dynamic power estimation techniques simulate the design using a large input vector set for accurate estimation. However, the simulation time is prohibitively long for bigger designs with larger vector sets. The statistical methods, on the other hand, use analytical tools that make them faster but less accurate. To achieve the accuracy of dynamic power estimation and the speed of statistical methods, one approach is to generate a compact, representative vector set that has the same switching transition behavior as the original larger vector set. The compaction algorithm presented in this paper uses fractal concepts to generate such a compact vector set. The fractal technique quantifies correlation by a fractal parameter which can be determined faster than calculating correlation explicitly. Experimental results on circuits from the ISCAS85 and ISCAS89 benchmark suites, with correlated input vector sets, resulted in a maximum compaction ratio of 65.57X (average 38.14X) and maximum power estimation error of 2.4% (average 2.06%). Since the size of the compact vector set used for simulation is smaller, the simulation time will be shorter and will significantly speed up the design cycle.

Simulation-based power estimation for low-power designs : A fractal approach

Low-power CMOS integrated circuit design requires accurate power estimation at every level in the hierar chy. In this paper, the Fractal Compaction Algorithm is presented. It is based on fractal concepts and is used to generate a compacted vector that allows fast, accurate simulation-based power estimation. Typi cally, power estimation methods are either dynamic or static. Dynamic methods simulate the design using specific input vector sets and estimate power. Though accurate, these methods require long simulation time for larger designs. Static power estimation methods, on the other hand, are based on analytical tools that estimate power quickly but with less accuracy. To achieve the accuracy of dynamic methods and the speed of static methods, one approach is to generate a com pact, representative vector set with switching behav ior similar to the original set. The algorithm gener ates a compact vector set by exploiting the correlation in the toggle distribution of the circuits internal nodes. Experiments on ISCAS85 benchmark circuits with a vector set size of 4000 results in a compaction of 65.57X (max) and 38.14X (avg) with power estimation error of 2.40% (max) and 2.06% (avg). The reduction in simu lation time translates into a shorter design phase and quicker tape out. Compaction results for various vec tor sizes are also presented.