Rajarshi Mukherjee

Multiple error diagnosis based on xlists

In this paper, we present multiple error diagnosis algorithms to overcome two significant problems associated with current error diagnosis techniques targeting large circuits: their use of limited error models and a lack of solutions that scale well for multiple errors. Our solution is based on a non-enumerative analysis technique, based on logic simulation (3-valued and symbolic), for simultaneously analyzing all possible errors at sets of nodes in the circuit. Error models are introduced in order to address the locality aspect of error location and to identify sets of nodes that are local with respect to each other. Theoretical results are provided to guarantee the diagnosis of modeled errors and robust diagnosis approaches are shown to address the cases when errors do not correspond to the modeled types. Experimental results on benchmark circuits demonstrate accurate and extremely rapid location of errors of large multiplicity.

Solving the latch mapping problem in an industrial setting

We describe a complete method for the latch mapping problem that is based on the efficient integration of previously proposed techniques for latch mapping as well as novel optimizations for further improvement. The highlights of the proposed approach include a new method of integrating complete methods and incomplete methods for latch mapping, the use of incremental reasoning to optimize the overall algorithm and the use of a conventional combinational equivalence checking tool as the core engine. Experiments confirm that the proposed method retains much of the efficiency and capacity of incomplete methods while providing the completeness of complete methods and derives significant performance improvements form the proposed optimizations.

Verification of an Industrial CC-NUMA Server

Directed test program-based verification or formal verification methods are usually quite ineffective on large cache-coherent, non-uniform memory access (CC-NUMA) multiprocessors because of the size and complexity of the design and the complexity of the cache-coherence protocol. A controllable biased/constrained random stimuli generator coupled with an error detection mechanism using scoreboards and feedback with coverage analysis tools is a promising alternative methodology. We applied this methodology to verify a shared memory and message passing multiprocessor system consisting of 32 and 64 bit processor-based symmetric multiprocessing (SMP) servers connected by a proprietary cache coherent router-based interconnect fabric. This paper describes the problems faced, solutions implemented, and design decisions taken to design the scoreboard and discusses the errors found by this methodology.

Hierarchical error diagnosis targeting RTL circuits

Diagnosis algorithms targeting design errors in RTL circuit descriptions are presented in this paper. The algorithms presented exploit the hierarchy available in RTL designs to locate design errors. Xlists are shown to be useful to capture the effects of design errors within components of RTL designs. Information from the simulation of Xlists is used to systematically diagnose components in error. Experiments are performed on RTL benchmark circuits using a prototype that we have developed to demonstrate the rapid and accurate location of errors. They also show that diagnosis at the RTL offers a significantly superior alternative to diagnosis at the gate-level both in terms of diagnostic accuracy and computational efficiency.

An efficient filter-based approach for combinational verification

We have developed a filter-based framework where several fundamentally different techniques can be combined to provide fully automated and efficient heuristic solutions to verification and possibly other NP-complete problems. Such an integrated methodology is far more robust and efficient than any single existing technique on a wide variety of circuits. Our methodology has been applied to verify the ISCAS 85 benchmark circuits and efficient verification results have been presented on a large set of industrial circuits which could not be verified using several published techniques and commercial verification tools available to us.

Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table

We propose a novel methodology that combines local BDDs with a hash table for very efficient verification of combinational circuits. The main purpose of this technique is to remove the considerable overhead associated with case-by-case verification of internal node pairs in typical internal correspondence based verification methods. Two heuristics based on the number of structural levels of circuitry looked at and the total number of nodes in the BDD manager are used to control the BDD sizes and introduce new cutsets based on already found equivalent nodes. We verify the ISCAS85 benchmark circuits and demonstrate significant speedup over existing methods. We also verify several hard industrial circuits and show our superiority in extracting internal equivalences.

Automatic partitioning for efficient combinational verification

A majority of the state-of-the-art combinational verification techniques are based on the extraction and use of internal equivalences between two circuits. Verification can become difficult if the two circuits have none or very few internal correspondences. In this paper we investigate automatic circuit partitioning as a methodology to make otherwise intractable circuits relatively tractable to the verifier. We show that given any two circuits to be verified, finding the best partitions that minimize the verification runtime is NP-hard. Therefore, we propose efficient heuristics to utilize certain characteristics of typical circuit design styles to find good partitions for the circuits. A key difference between our approach and earlier approaches to circuit partitioning is that ours is fully automated and does not require any prior knowledge of the type of function being implemented by the circuit. Using circuit partitioning we are able to verify several hard industrial circuits that could not be verified otherwise.

An efficient solution to the storage correspondence problem for large sequential circuits

Traditional state-traversal-based methods for verifying sequential circuits are computationally infeasible for circuits with a large number of memory elements. However, if the correspondence of the memory elements of the two circuits can be established, a difficult sequential verification problem can be transformed into an easier combinational verification problem. In this paper, we propose an approach that combines two complementary simulation-based methods for fast and accurate storage correspondence. Experiments on the large ISCAS89 benchmark circuits demonstrate the superiority.