Koichiro Takayama

Model Checking Based on Sequential ATPG

State-space explosion remains to be a significant challenge for Finite State Machine (FSM) exploration techniques in model checking and sequential verification. In this work, we study the use of sequential ATPG (Automatic Test-Pattern Generation) as a solution to overcome the problem for a useful class of temporal logic properties. We also develop techniques to exploit the existence of synchronizing sequences to reduce some temporal logic properties to simpler properties that can be efficiently checked using an ATPG algorithm. We show that the method has the potential to scale up to large, industrial-strength, hardware designs for which current model checking techniques fail.

A method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulator

A method is presented to accelerate test generation, which synthesizes a test-generation circuit S(C, F) that combines the original combinational circuit C (modified by programmable faults F) and peripheral circuits that automatically generate a test of C. The test patterns are generated by searching the inputs to expose faults to the outputs using an ultrahigh-speed simulator (SP).<<ETX>>

Effective safety property checking using simulation-based sequential ATPG

In this paper, we present a successful application of a simulation-based sequential Automatic Test Pattern Generation (ATPG) for safety property verification, with the target on verifying safety property of large, industrial strength, hardware designs for which current formal methods fail. Several techniques are developed to increase the effectiveness and efficiency during state exploration and justification of the test generator for verification, including (1) incorporation of a small combinational ATPG engine, (2) reset signal masking, (3) threshold-value simulation, and (4) weighted Hamming distance. Experimental results on both ISCAS89 benchmark circuits and real industry circuits have shown that this simulation-based verifier achieves better or comparable results to current state-of-the-art formal verification tools BINGO and CHAFF.

A retargetable VLIW compiler framework for DSPs with instruction-level parallelism

A standard design methodology for embedded processors today is the system-on-a-chip design with potentially multiple heterogeneous processing elements on a chip, such as a very long instruction word (VLIW) processor, digital signal processor (DSP), and field-programmable gate array. To be able to program these devices, we need compilers that are capable of generating efficient code for the different types of processing elements with efficiency measured in terms of power, area, and execution time. In addition, the compilers should also be highly retargetable to enable the system designer to quickly evaluate different cores for the application on hand and reduce the time to market. In this paper, we show that we can extend a conventional VLIW compilation environment to develop highly retargetable optimizing compilers for DSPs with irregular architectures. We have used the second generation Fujitsu Hiperion fixed-point DSP as our primary example to evaluate the compiler framework. We demonstrate through experimental results that execution time for the assembly code generated using our framework is roughly two times better than that of the code generated by a widely used commercially available DSP compiler. Even without incorporating DSP-specific optimizations in our extended VLIW framework, we demonstrate that the compiled code has a better performance than the code generated by a commercial DSP-specific compiler in all our examples.

A new functional test program generation methodology

This paper introduces a new method for manually generating test programs to validate a processor design. Current manual methods do not utilize high level of abstraction for describing test programs and lack many important features like reusability, incremental validation, and test program compaction; they also work on a formal model specifically developed for validation purposes. To solve the above problems, we use test specification expressions to describe test programs and generate test sequences based on an instruction-set description of a processor written for synthesis purposes. We provide experimental results of generating test programs for several processors to show the effectiveness of our method.

An efficient filter-based approach for combinational verification

We have developed a filter-based framework where several fundamentally different techniques can be combined to provide fully automated and efficient heuristic solutions to verification and possibly other NP-complete problems. Such an integrated methodology is far more robust and efficient than any single existing technique on a wide variety of circuits. Our methodology has been applied to verify the ISCAS 85 benchmark circuits and efficient verification results have been presented on a large set of industrial circuits which could not be verified using several published techniques and commercial verification tools available to us.

Software Defect Prediction for LSI Designs

While mining software repositories is a field which has greatly grown over the last ten years, Large Scale Integrated circuit (LSI) design repository mining has yet to reach the momentum of softwares. We felt that it represents untouched potential especially for defect prediction. In an LSI, referred to as hardware later on, verification has a high cost compared to design. After studying existing software defect prediction techniques based on repository mining, we decided to adapt some for hardware design repositories in the hope of saving precious resources by focusing design and verification effort on the most defect prone parts of the design. By focusing our resources on the previously mentioned parts, we hope to improve our designs quality. We discuss how we applied these prediction techniques to hardware and show our results are promising for the future of hardware repository mining. Our results allowed us to estimate a possible total verification time reduction of 12%.

Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table

We propose a novel methodology that combines local BDDs with a hash table for very efficient verification of combinational circuits. The main purpose of this technique is to remove the considerable overhead associated with case-by-case verification of internal node pairs in typical internal correspondence based verification methods. Two heuristics based on the number of structural levels of circuitry looked at and the total number of nodes in the BDD manager are used to control the BDD sizes and introduce new cutsets based on already found equivalent nodes. We verify the ISCAS85 benchmark circuits and demonstrate significant speedup over existing methods. We also verify several hard industrial circuits and show our superiority in extracting internal equivalences.

Automatic partitioning for efficient combinational verification

A majority of the state-of-the-art combinational verification techniques are based on the extraction and use of internal equivalences between two circuits. Verification can become difficult if the two circuits have none or very few internal correspondences. In this paper we investigate automatic circuit partitioning as a methodology to make otherwise intractable circuits relatively tractable to the verifier. We show that given any two circuits to be verified, finding the best partitions that minimize the verification runtime is NP-hard. Therefore, we propose efficient heuristics to utilize certain characteristics of typical circuit design styles to find good partitions for the circuits. A key difference between our approach and earlier approaches to circuit partitioning is that ours is fully automated and does not require any prior knowledge of the type of function being implemented by the circuit. Using circuit partitioning we are able to verify several hard industrial circuits that could not be verified otherwise.

A high-speed test-generation method using a test generation circuit

This paper discusses the test-generation circuit which automatically generates a test pattern for a combinational circuit. The test-generation circuit is designed so that two algorithms of automatic test generation and fault simulation can be executed by the circuit. The test pattern for the circuit under test is generated at a high speed by simulating the operation of the test-generation circuit using the dedicated logic simulation machine SP. As a result of performance evaluation for the well known benchmark circuits, the test-generation circuit was constructed with eleven times the number of SP elements on the average compared with the circuit under test. By a simulation using only one SP processor, the operation of the test-generation circuit could be simulated at 6 kHz on the average. Thus, it is seen that the test pattern for the circuit under test can be generated with a high fault coverage with a speed surpassing the software on a large-scale computer. The method proposed herein is to apply effectively the architecture of the dedicated machine for a high-speed logic simulation to the search problem such as test generation. Thus, the validity of the idea was verified.