Rajarshi Mukhopadhyay

A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS

In this paper, we present a 39.1-to-41.6 GHz 1.2 V 64 mW DeltaSigma fractional-N frequency synthesizer that is implemented in 90nm CMOS. To reduce power consumption, a divide-by-4 injection-locking frequency divider (ILFD) is used in the feedback loop and a digital calibration technique is implemented to overcome the ILFD locking-range limitations.

25.1 A 50.7% peak efficiency subharmonic resonant isolated capacitive power transfer system with 62mW output power for low-power industrial sensor interfaces

Low-power sensor interfaces play a key role in monitoring industrial system reliability in hostile environments. They are exposed to destructive surge voltages, which are caused by ground current spikes from operation transitions of machinery and motor drives, endangering circuit functionality. Employing galvanic isolation is thus imperative to protect the sensor analog front end (AFE) from severe damage. However, the use of an isolation barrier presents several challenges. Without a wired connection to the sensor AFE, power/data must be transferred through the barrier via magnetic or capacitive coupling. Moreover, size and cost are constrained in such applications. In [1], an isolated DC/DC converter is used, which delivers up to 2W with 80% efficiency, but at the cost of bulky external micro-henry transformers. To avoid a large form-factor solution, the transformers can be integrated, but efficiency is sacrificed and cost is added. In [2–3], the operating frequency of the integrated transformers is ∼300MHz for size reduction. However, at such a high frequency, the switching power loss (PSW) is greater than 10s of mW, reducing efficiency below 30%. On the other hand, capacitive isolation, usually used in digital links [4], replaces polyimide-based transformers with integrated thick dielectric capacitors. It represents a major improvement due to size and cost savings as a result of integration on silicon.

Total Ionizing Dose Effects on a High-Voltage (>30V) Complementary SiGe on SOI Technology

Total ionizing dose (TID) effects are evaluated for a high-voltage (>30 V) complementary SiGe on SOI technology. Devices are irradiated with 10-keV X-rays at doses up to 5 Mrad(SiO2). The results depend strongly on collector-to-emitter bias, in both forward- and inverse-mode. An anomalous reduction in current gain at high injection in forward-mode operation is observed at doses >500 krad(SiO2). Calibrated 2-D TCAD simulations suggest that this high injection phenomenon is primarily due to interface traps near the STI/Si interface, which is exhibited as a collector resistance increase in the forward Gummel characteristics. Additionally, a strong collector doping dependence is observed, which indicates that this is primarily driven by the thick and lightly doped collector used in this technology. These results illustrate, that high concentrations of interface traps at the STI can have a strong impact on the forward-mode TID response of SiGe HBTs.