Rajdeep Bondade

Enabling Power-Efficient DVFS Operations on Silicon

With the perpetual power increase in modern VLSI systems, efficient and effective power management has been critical to next-generation IC designs. To overcome this grand challenge, techniques, such as dynamic voltage/frequency scaling (DVFS), have been proposed to jointly optimize power, energy and operating performance, leading to significantly improved system reliability, efficiency and battery lifetime. From both system-level and circuit-level perspectives, this paper investigates key design issues, control schemes, circuit architectures and future research directions, involved in the development of application-aware, multiple- and variable-output DC-DC power converters. The article first discusses key multiple-output converters such as the single-inductor multiple-output (SIMO) DC-DC converters and their system-level integration for DVFS power management, followed by our investigation on various adaptive-output power converter topologies and corresponding design challenges. The paper also addresses the importance of hardware-software co-design for future power management systems. With the integration of the enabling hardware platform, power processing, in addition to the traditional signal processing, rises to become another key factor to next-generation VLSI designs. This naturally enables effective on-chip power tracking, power processing and thermal monitoring. More importantly, it would significantly change traditional design concepts and largely benefit signal processing in return, eventually leading to revolutionary changes on system reliability, performance, efficiency and operating lifetime.

Reconfigurable Switched-Capacitor Power Converters

The proliferation of self-powered devices and implantable biomedical microsystems has led to the growth of highly-efficient, multi-mode power supply designs. SC power converters are invaluable to such applications since they enable robust operation at ultra-low-power levels, enhance the operation lifetime and achieve monolithic implementation, thereby reducing the size, cost and PCB footprint of the overall system.

Leveraging temporal and spatial separations with the 24-hour knowledge factory paradigm

The 24-H Knowledge Factory facilitates collaboration between geographically and temporally distributed teams. The teams themselves form a strategic partnership whose joint efforts contribute to the completion of a project. Project-related tasks are likewise distributed, allowing tasks to be completed on a continuous basis, regardless of the constraints of any one team’s working hours. However, distributing a single task between multiple teams necessitates a handoff process, where one team’s development efforts and task planning are communicated from one team ending their shift to the next that will continue the effort. Data management is, therefore, critical to the success of this business model. Efficiency in data management is achieved through a strategic leveraging of key tools, models, and concepts.

Self-Reconfigurable Channel Data Buffering Scheme and Circuit Design for Adaptive Flow Control in Power-Efficient Network-on-Chips

This paper presents a self-reconfigurable channel data buffering scheme and circuit design for next-generation network-on-chips (NoCs). The design is optimized for power efficiency and data throughput, from system to circuit level. During network congestion, the buffering scheme realizes adaptive flow control by reconfiguring the channel buffers for online data storage. Once congestion is alleviated, data transmission resumes from the foremost buffer stage, thereby improving NoC throughput. It also achieves system-level power optimization through an integrated hardware-software codesign approach. Using software techniques such as dynamic voltage and frequency scaling, optimal voltages and frequencies are provided to the system through a hardware-based single-inductor multiple-output dc-dc converter platform. Meanwhile, power dissipation is further minimized through switched-capacitor delay control modules. A CMOS IC prototype has been fabricated, with 16-bit data transmission capability. It demonstrates 58.9% power saving over conventional designs. To achieve the same throughput, it consumes only 45.4% power of the best prior art. The flexibility of the buffering scheme, along with the integrated power management solution, allows it to be applied to most existing commercial NoC architectures.

Design of Integrated Bipolar Symmetric Output DC–DC Power Converter for Digital Pulse Generators in Ultrasound Medical Imaging Systems

This paper presents a bipolar symmetric output switching dc-dc converter for digital pulse generators in ultrasound medical imaging systems. The proposed power stage architecture can generate symmetric bipolar supply voltages, while operating in a time-interleaving manner. Meanwhile, in order to power unipolar pulse generators with the same peak-to-peak pulse amplitude, the power stage can also be reconfigured to deliver a 2× unipolar output voltage. The power converter employs an adaptive ΔI charge balance control scheme to ensure that the outputs are symmetrically balanced and well regulated. At the circuit level, to utilize a single feedback controller for both power stage topologies, the assignment of a suitable chip ground is discussed. A prototype is fabricated using a 0.25-μm CMOS process and occupies a chip area of 6 mm 2. For an input supply voltage of 1.5 V, the dc-dc converter can regulate the bipolar outputs at a nominal voltage level of ±2.5 V and at 5 V for the unipolar output configuration and a maximum load current of 45 mA for both. The bipolar output power converter achieves a maximum efficiency of 83.4% at a load power of 187.5 mW, with the voltage balance error maintained within ± 2% over the entire load range.

Hardware-Software Codesign of an Embedded Multiple-Supply Power Management Unit for Multicore SoCs Using an Adaptive Global/Local Power Allocation and Processing Scheme

Power dissipation has become a critical design constraint for the growth of modern multicore systems due to increasing clock frequencies, leakage currents, and system parasitics. To overcome this urgent crisis, this article presents an embedded platform for on-chip power management of a multicore System-on-Chip (SoC). The design involves the development of two key components, from the hardware to the software level. From the hardware perspective, a multiple-supply power management unit is proposed and is implemented using a Single-Inductor Multiple-Output (SIMO) DC-DC converter. To dynamically respond to the sensed instantaneous power demands and to accurately control the power delivery to the processor cores, the power management unit employs a software-defined adaptive global/local power allocation feedback controller. The proposed controller is designed using the hardware-software codesign methodology to uniquely control the SIMO converter during various operation scenarios. This is achieved using several embedded software control algorithms that operate synergetically to ensure efficient and reliable system operation. The hardware-software codesign technique also allows the SIMO controller to be integrated with future microprocessor cores. Therefore, by employing the vast amount of on-chip resources, the converter can perform effective power processing to provide the most power-optimal voltages at the hardware level. Such an embedded power management module leads to an integrated, power-aware, and autonomous SoC design that is independent of additional external hardware control, thereby reducing on-chip area and system complexity. In this design, each power output from the SIMO converter provides a step-up/down voltage conversion, thereby enabling a wide range of variable supply voltage. An adaptive global/local power allocation control algorithm is employed to significantly improve Dynamic Voltage and Frequency Scaling (DVFS) tracking speed and line/load regulation, while still retaining low cross-regulation. Designed with a 180nm CMOS process, the converter precisely provides three independently variable power outputs from 0.9 V to 3.0 V, with a total power range from 33 mW to 900 mW. A very fast load transient response of 3.25 μs is achieved, in response to a 67.5-mA full-step load current change. The design thus provides a cost-effective power management solution to achieve a robust, fast-transient, DVFS-compatible multicore SoC.

An integrated SIDO boost power converter with adaptive freewheel switching technique

This paper presents a single-inductor dual-output (SIDO) boost DC-DC converter with an adaptive freewheel switching technique. Due to the adoption of freewheel switching duration averaging, the optimal freewheel durations in each phase of the SIDO converter are acquired within one switching cycle. The optimal freewheel switching duration improves the efficiency of the SIDO converter, especially during unbalanced load conditions, by reducing the conduction losses due to the lossy freewheel switch. The proposed controller also accelerates the freewheel switching current adjustment process during the load transient periods. The proposed converter, operating in the pseudo-continuous conduction mode (PCCM), has been verified through fully transistor-based HSPICE simulation results, with a 130-nm CMOS process. It achieves a maximum efficiency of 90.1%, at an output power of 430 mW and a switching frequency of 500 kHz. For a load change from 100 mA to 50 mA, the proposed technique reduces the conduction losses during the freewheel switching duration by 99.52%, compared with the traditional methods.

A linear-assisted DC-DC hybrid power converter for envelope tracking RF power amplifiers

This paper presents the design of a linear-assisted hybrid DC-DC power converter for envelope tracking RF power amplifiers. To jointly leverage the high efficiency of switch-mode DC-DC converters and the wide bandwidth capabilities of linear regulators, a hybrid power supply topology is employed. It exploits a parallel combination of a switch-mode buck DC-DC converter to provide the average power required by the PA, while a push-pull linear regulator is activated to quickly respond to load transients and for envelope tracking. The proposed power supply was designed with a TSMC 0.35-μm CMOS process. For an input voltage of 3V, the PA supply voltage can be regulated at any voltage level from 0.5V to 2.5V, at a nominal switching frequency of 10MHz. It achieves a maximum efficiency of 91.7% at 500mW.

A DLL-regulated SIMO power converter for DVS-enabled power-aware VLSI systems

A delay-locked loop (DLL) regulated single-inductor multiple-output (SIMO) power converter is presented. It takes advantage of the fast phase locking property of a DLL to identify the SIMO converters regulation errors between the output voltages and their corresponding references. In response to these errors, an adaptive peak current modulation technique is proposed to adjust the instantaneous duty ratios, and thus minimize the regulation errors in the converter. The DLL acquires locking within 350 ns, allowing it to respond to load dynamics promptly, which is very desirable for DVS-enabled power-efficient VLSI systems. The system was designed and simulated in IBM 130-nm CMOS process. Fully transistor-based HSPICE simulations show that, with a 1.8 V nominal input supply, the converter precisely regulates two independent output voltages at 0.9 V and 1.5 V, respectively. It achieves the maximum efficiency of 87.2% at a total power of 104.8 mW and a switching frequency of 500 kHz.

Fundamental Charge Pump Topologies and Design Principles

Switched-capacitor (SC) DC–DC converters are a class of power converters that are used to convert one voltage level to another, through the use of switches and capacitors. They consist of two parts, a power stage, which is also known as a charge pump, and a feedback/feed-forward controller that regulates the output to the desired voltage value.