Rajeev Jayaraman

A novel predictable segmented FPGA routing architecture

In the development of new FPGA architectures, a designer must balance speed, density and routing flexibility. In this paper, we discuss a new FPGA architecture based on a patented [1], novel, segmented routing fabric that is targeted to high performance and predictability but does not sacrifice routability or area efficiency. Current segmented architectures allow much flexibility in routing, but incur large delay penalties when a signal has high fanout or must traverse medium to long distances to reach its target. Reducing the number of programmable interconnect points (PIPs) that a signal must traverse to reach its target, while eliminating the RC delay buildup due to signal fanout, improves design performance and offers highly predictable signal delays.

Physical design for FPGAs

FPGAs have been growing at a rapid rate in the past few years. Their ever-increasing gate densities and performance capabilities are making them very popular in the design of digital systems. In this paper we discuss the state-of-the-art in FPGA physical design. Compared to physical design in traditional ASICs, FPGAs pose a different set of requirements and challenges. Consequently the algorithms in FPGA physical design have evolved differently from their ASIC counterparts. Apart from allowing FPGA users to implement their designs on FPGAs, FPGA physical design is also used extensively in developing and evaluating new FPGA architectures. Finally, the future of FPGA physical design is discussed along with how it is interacting with the latest FPGA technologies.

(When) will FPGAs kill ASICs? (panel session)

There was a time - in the dim historical past - when foundries actually made ASICs with only 5000 to 50,000 logic gates. But FPGAs and CPLDs conquered those markets and pushed ASIC silicon toward opportunities with more logic, volume, and speed. Todays largest FPGAs approach the few-million-gate size of a typical ASIC design, and continue to sprout embedded cores, such as CPUs, memories, and interfaces. And given the risks of nonworking nanometer silicon, FPGA costs and time-to-market are looking awfully attractive. So, will FPGAs kill ASICs? ASIC technologists certainly think not. ASICs are themselves sprouting patches of programmable FPGA fabric, and pushing new realms of size and especially speed. New tools claim to have tamed the convergence problems of older ASIC flows. Is the future to be found in a market full of FPGAs with ASIC-like cores? ASICs with FPGA cores? Other exotic hybrids? Our panelists will share their disagreements on these prognostications.

Performance Improvements through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs

Platform FPGAs have introduced complex reconfigurable black-boxes for complete system on chip implementation. With rising expectations from these architectures there is a need to perform optimizations across the FPGA slice fabric and the newly introduced black boxes to maximize performance gains. In this paper, we discuss a timing driven reconfiguration technique to improve performance of DSP designs on platform FPGAs by (i) optimal register placement algorithms within the DSP 48 block and (ii) timing driven mechanism to have maximal pipeline depth.

ICCAD and Xilinx

This paper examines the unique impact of Computer-Aided Design on Xilinx and on Field Programmable Gate Arrays. A brief history and description of FPGA implementation software is given. Some specific CAD algorithms that have influenced FPGA implementation software are listed along with their contributions.