Rajender Kumar Sharma

Detection/ estimation of adulteration in gasoline and diesel using ultrasonics

The exhaust gases from fast increasing number of automobiles is a major source of urban air pollution in third world countries. Adulteration of gasoline and diesel further aggravates the problem. For the prevention of adulteration, monitoring of fuel quality at the distribution point, therefore, is essential. In this paper the feasibility of detection/estimation of adulteration in gasoline and diesel using ultrasonic radiations has been proposed. The speed of ultrasound in non-adulterated and intentionally adulterated gasoline and diesel has been determined using pulse echo method. It has been observed that adulteration results in the change in the measured speed of ultrasound which can be calibrated in terms of percentage adulteration.

An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm

Floating point multiplication is a crucial operation in high power computing applications such as image processing, signal processing etc. And also multiplication is the most time and power consuming operation. This paper proposes an efficient method for IEEE 754 floating point multiplication which gives a better implementation in terms of delay and power. A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is used to implement unsigned binary multiplier for mantissa multiplication. The multiplier is implemented using Verilog HDL, targeted on Spartan-3E and Virtex-4 FPGA.

An Energy Efficient Logic Approach to Implement CMOS Full Adder

An energy efficient internal logic approach for designing two 1-bit full adder cells is proposed in this work. It is based on decomposition of the full adder logic into the smaller modules. Low power, high speed and smaller area are the main features of the proposed approach. A modified power aware NAND gate, an essential entity, is also presented. The proposed full adder cells achieve 30.13% and improvement in their power delay product (PDP) metrics when compared with the best reported full adder design. Some of the popular adders and proposed adders are designed with cadence virtuoso tool with UMC 90nm technology operating at 1.2V supply voltage and UMC 55nm CMOS technology operating at 1.0V. These designs are tested on a common environment. During the experiment, it is also found that the proposed adder cells exhibit excellent signal integrity and driving capability when operated at low voltages.

A method of REM-NREM sleep distinction using ECG signal for unobtrusive personal monitoring

Computers are used extensively in sleep labs for polysomnography and for assistance in sleep staging. However, the test is highly inconvenient to the patient and requires availability of specially equipped sleep labs. Alternative approaches that enable unobtrusive in-home sleep staging with ECG or other signals are highly desirable. In this paper we describe a method that can be used for distinction of REM and NREM sleep stages using spectral and non-linear features of ECG derived RR interval series. To test the accuracy of the system, we extracted the RR interval series from sleep studies of 20 young healthy individuals. Time domain, spectral and non-linear features were computed and tested for discriminability. Features showing high degree of discrimination were selected. A polynomial support vector machine was trained with selected features - percent power in HF band, LF/HF, Poincare plot parameters, exponents from Detrended fluctuation analysis, and sampEn of the half of the signals. The hyperplane was used to classify the other half of the data. The results show an accuracy of 76.25% with Cohens kappa as 0.52 for a two-class model of five minute signal. The results dropped to 72.8% accuracy and k=0.48 for the two class model of one minute signal. The minimal set offers a reasonable trade-off for possible in-home monitoring, at least for some conditions that require only REM-NREM distinction. The method after extensive trials and standardisation, can alleviate the load of special purpose PSG labs and enable the tests to be done on general purpose computers.

Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications

Floating point multiplication is one of the crucial operations in many application domains such as image processing, signal processing etc. But every application requires different working features. Some need high precision, some need low power consumption, low latency etc. But IEEE-754 format is not really flexible for these specifications and also design is complex. Optimal run-time reconfigurable hardware implementations may need the use of custom floating-point formats that do not necessarily follow IEEE specified sizes. In this paper, we present a run-time-reconfigurable floating point multiplier implemented on FPGA with custom floating point format for different applications. This floating point multiplier can have 6 modes of operations depending on the accuracy or application requirement. With the use of optimal design with custom IPs (Intellectual Properties), a better implementation is done by truncating the inputs before multiplication. And a combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is used to implement unsigned binary multiplier. This further increases the efficiency of the multiplier.

Area efficient diode and on transistor inter-changeable power gating scheme with trim options for SRAM design in nano-complementary metal oxide semiconductor technology

Reducing the leakage power in embedded static random access memory (SRAM) memories is critical for low-power applications. Raising the source voltage of SRAM cells through diode transistor in standby mode reduces the leakage currents effectively. However, in order to preserve the state of the cell in standby mode, the source voltage cannot be raised beyond a certain level. To achieve that, the size of the required diode transistor becomes larger, as the supply voltage shrinks in the nano-complementary metal oxide semiconductor (CMOS) technologies. In this work, an area efficient power gating technique with capability of post-silicon trimming of the voltage across SRAM cell is presented. Proposed scheme provides many options to trim the SRAM source voltage (ranging from 50 to 150 mV in steps of 25 mV approximately.) with 3% area overhead when applied to complete SRAM bank. The scheme has been illustrated with a 16 kb SRAM macro at 28 nm CMOS technology at 0.85 V supply voltage. Sector-based power gating is presented which enables leakage savings while memory is in the active mode. The area overhead of the presented scheme is 8% when applied to SRAM bank array split into sectors.

Double fault tolerant full adder design using fault localization

In the era of advanced microelectronics, rate of chip failure is increased with increased in chip density. A system must be fault tolerant to decrease the failure rate. The presence of multiple faults can destroy the functionality of a full adder and there is a trade-off between number of fault tolerated and area overhead. This paper presents an area efficient fault tolerant full adder design that can repair single and double fault without interrupting the normal operation of a system. In this approach, self checking full adder is used detecting the fault based on internal functionality. This makes the method efficient in term of area and number of fault tolerated when compared to the existing designs.

Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing

To develop low-power, high-speed and area-efficient design for portable electronics devices and signal processing applications is a very challenging task. Multiplier has an important role in digita...

Disease detection using voice analysis: a review

Disease detection using voice analysis is a vital research topic in medical engineering. It is a reliable, efficient, economic and easy to use method. It also helps to detect the diseases at its earlier stage. Voice features are extracted using some DSP techniques. These features contain information on health of voice tract and of the organs cooperating in speech production. These features represent the particular voice and may be used to discriminate voice of healthy and unhealthy persons. The time domain analysis, spectrum analysis, cepstrum analysis, glottal waveform analysis are used to extract the voice features. These features are then classified into groups using various classification techniques like vector quantisation, dynamic time wrapping, support vector machine, Gaussian mixture model and artificial neural network. This paper described all these techniques in detail.

A new energy efficient full adder design for arithmetic applications

In the era of advanced microelectronics, designing an energy efficient processor is a prime concern. Full adder is a most crucial unit in digital signal processing applications. This paper addresses the implementation of 1-bit full adder cell. In addition to this, AND and OR gate as an essential entity is also proposed with minimum hardware overhead. The circuit being studied is implemented using Cadence Virtuoso tool in 55-nm CMOS process technology. The simulations are carried out using spectre simulator under various conditions such as different operating frequencies, load capacitors and supply voltages that may occur in realistic conditions. In comparison with the C-CMOS full adder design, the proposed implementation was found to offer 50.24% improvement in power consumption and 26.46% improvement in power delay metric.