Rajendran Nair
Intel
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Rajendran Nair.
international solid-state circuits conference | 2002
Siva G. Narendra; M. Haycock; V. Govindarajulu; Vasantha Erraguntla; Howard Wilson; Sriram R. Vangal; Amaresh Pangal; E. Seligman; Rajendran Nair; Ali Portland Keshavarzi; Bradley Bloechel; Gregory E. Dermer; R. Mooney; Nitin Borkar; S. Borkar; Vivek De
A router chip, that incorporates on-chip forward body biasing capability with 2% area overhead, achieves 1 GHz operation at 1.1 V supply in a 150 nm logic technology, compared to 1.25 V required for the original design having no body bias. Switching power is 23% less and chip leakage is reduced by 3.5/spl times/ in standby mode by withdrawing forward bias.
symposium on vlsi circuits | 2002
J. Tschanz; Siva G. Narendra; Rajendran Nair; Vivek De
Test chip measurements show that adaptive V/sub CC/ is useful for reducing impacts of parameter variations on frequency, active power and leakage power of microprocessors. Using adaptive V/sub CC/ together with adaptive V/sub BS/ or WID-V/sub BS/ is much more effective than using any of them individually.
Archive | 2001
Rajendran Nair; David GenLong Chow
Archive | 1999
Ali Keshavarzi; Vivek De; Tanay Karnik; Rajendran Nair
Archive | 1999
James T. Kao; Vivek De; Siva G. Narendra; Rajendran Nair
Archive | 2000
Rajendran Nair; Chantal Wright
Archive | 1998
Rajendran Nair; Mark A. Beiley; Morteza Afghahi
Archive | 2000
Rajendran Nair; Chantal Wright; Stephen R. Mooney; Siva G. Narendra
Archive | 2000
Rajendran Nair; Stephen R. Mooney
Archive | 2000
Joseph T. Kennedy; Stephen R. Mooney; Aaron K. Martin; Rajendran Nair