Gilroy Vandentop

Optical I/O technology for digital VLSI

We describe the development of a high-speed, 12-channel (8-data, 2-clock and 2-alignment channels), parallel optical link with a unique packaging concept. The package is used to demonstrate the viability of chip-to-chip optical I/O in very large scale integration (VLSI) circuits. However, for implementation of optical systems in high performance computing applications, the cost of components and packaging has to come down significantly from the traditional optical communication distances. In the current work we attempted to realize such a system by using power efficient optical and electronic components together with a potentially low cost packaging solution compatible with the electronics industry. Vertical Cavity Surface Emitting Lasers (VCSEL), positive-intrinsic-negative (PIN) photodetectors, polymer waveguide arrays as well as CMOS transceiver chip were heterogeneously integrated on a standard microprocessor flip-chip pin grid array (FCPGA) substrate. The CMOS transceiver chip from 0.18μm processing technology contains VCSEL drivers, transimpedance and limiting amplifiers and on-chip self-testing circuits. A self-test circuit in such high-speed systems will be highly beneficial to reduce the testing cost in real products. For fully assembled packages we measured a 3 Gb/s optical eye for the transmitter (24Gb/s aggregate data rate) and a transmission over the complete link was achieved at 1 Gb/s (8Gb/s aggregate data rate).

Sea of leads compliant I/O interconnect process integration for the ultimate enabling of chips with low-k interlayer dielectrics

Sea of leads (SoL) process integration for the series of steps required to transform a fully intact die at the wafer level to a die that is assembled onto a board is described. The primary goal is to address the issues involved in reconciling the fabrication and assembly requirements of compliant leads, such as SoL, with those of standard semiconductor processes and chip assembly techniques. The effort is motivated in-part by the potential failure of the low-k interlayer dielectric in microprocessors as a result of high mechanical stresses due to the coefficient of thermal expansion (CTE) mismatch between the chip and the board. SoL, and other compliant interconnections, mitigate this problem by mechanically decoupling the chip and the board. While compliant leads offer advantages over C4 technology, there is much to consider during the series of steps needed to transform the fully intact dice at the wafer level to dice that are assembled onto the board. The use of an encapsulation film over the leads during wafer sawing is shown to be necessary for slippery leads and other free-standing compliant leads. The use of a suitable flux when the leads are finished with a nickel-oxide nonwettable layer is essential for a successful wafer-level solder reflow. Successful die assembly using thermocompression bonding is demonstrated using two different SoL dice with correspondingly different substrates. The resistance of a chain of 30 cascaded leads is 2.7 /spl Omega/.

EUV Mask Process Development and Integration

It becomes increasingly important to have an integrated process for Extreme UltraViolet (EUV) mask fabrication in order to meet all the requirements for the 32 nm technology node and beyond. Intel Corporation established the EUV mask pilot line by introducing EUV-specific tool sets while capitalizing on the existing photomask technology and utilizing the standard photomask equipment and processes in 2004. Since then, significant progress has been made in many areas including absorber film deposition, mask patterning optimization, mask blank and patterned mask defect inspection, pattern defect repair, and EUV mask reflectivity metrology. In this paper we will present the EUV mask process with the integrated solution and the results of the mask patterning process, Ta-based in-house absorber film deposition, absorber dry etch optimization, EUV mask pattern defect inspection, absorber defect repair, and mask reflectivity performance. The EUV resist wafer print using the test masks that are fabricated in the EUV mask pilot line will be discussed as well.

Demonstration of full-field patterning of 32 nm test chips using EUVL

EUV lithography is considered one of the options for high volume manufacturing (HVM) of 16 nm MPU node devices [1]. The benefits of high k1(~0.5) imaging enable EUVL to simplify the patterning process and ease design rule restrictions. However, EUVL with its unique imaging process - reflective optics and masks, vacuum operation, and lack of pellicle, has several challenges to overcome before being qualified for production. Thus, it is important to demonstrate the capability to integrate EUVL into existing process flows and characterize issues which could hamper yield. A patterning demonstration of Intels 32 nm test chips using the ADT at IMEC [7] is presented, This test chip was manufactured using processes initially developed with the Intel MET [2-4] as well as masks made by Intels mask shop [5,6]. The 32 nm node test chips which had a pitch of 112.5 nm at the trench layer, were patterned on the ADT which resulted in a large k1 factor of 1 and consequently, the trench process window was iso-focal with MEEF = 1. It was found that all mask defects detected by a mask pattern inspection tool printed on the wafer and that 90% of these originated from the substrate. We concluded that improvements are needed in mask defects, photospeed of the resist, overlay, and tool throughput of the tool to get better results to enable us to ultimately examine yield.

Engineering the effective CTE of Si die with a T2 package

With the continuous scaling of low k dielectric in multicore processors, the intrinsic CTE mismatch between a Si die (CTE: 2.3 ppm/°C) and an organic substrate (16-18 ppm/°C) brings a susceptibility for more failures. There are limited successes in the engineering of the CTE of substrate with ceramic (~6 ppm/°C) or low CTE organic substrates (~12 ppm/°C). The CTE mismatch also contributes to solder joint reliability risks and misalignment in assembly. In this paper, we propose a very different method to address the CTE mismatch: the effective CTE of Si is engineered to match that of an organic substrate instead. The T2 package with both thinner die and thinner thermal interface material (TIM) is proposed as both a mechanical and thermal solution for electronic packages. Experimental measurement using DIC (digital image correlation) shows that the effective CTE of silicon can be as high as 15-16 ppm/°C. Thus, it reduces the mismatch between the silicon die and the organic substrate from roughly 15 ppm/°C to 1-3 ppm/°C. Moiré measurement shows the corner stress reduction and the temperature cycle study proves the effectiveness of CTE engineering. Thermomechanical simulations and reliability studies with different Si die thicknesses are also reported.

CD correction for half pitch 2x-nm on extreme ultraviolet lithography

This paper describes the critical dimension (CD) accuracy of metal-layer patterns for the 15-nm logic node and beyond replicated with model-based optical proximity correction, flare variation compensation, and shadowing effect correction. The model fitting took resist shrinkage during CD measurements into account so as to reduce the modeling error. Since sufficient accuracy was obtained for various patterns under the assumptions of device production, and since conventional illumination could be used, it was possible to establish a design rule with few restrictions for the 15-nm node. For the 12-nm logic node, an SRAM pattern for a cell size of 0.0288 μm2 was fabricated using dipole illumination. Advanced pre-production optics were used to assess the impact of flare on CD variation. Since chemical flare occurs in SSR4, a top coating was used to prevent acid re-adsorption during the post-exposure bake. The flare due to the optics was reduced to half that of conventional optics, and the CD variation due to flare was found to be predictable from the point spread function of the projection optics. This means that the established concept of flare correction is usable with advanced optics.