Rajesh A. Thakker

Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization

This paper presents application and effectiveness of Hierarchical particle swarm optimization (HPSO) algorithm for automatic sizing of low-power analog circuits. For the purpose of comparison, circuits are also designed using PSO and Genetic Algorithm (GA). CMOS technologies from 0.35 µm down to 0.13 µm are used. PVT (process, voltage, temperature) variations are considered during the design of circuits. We show that HPSO algorithm converges to a better solution, compared to PSO and GA. For CMOS Miller OTA, even performance of the circuit designed by HPSO algorithm is better than the performance of recently reported manually designed circuit. For the first time, design of this OTA, in 0.4 V supply voltage, is also presented. For this new design, HPSO algorithm has taken 23.5 minutes of CPU time on a Sun system with1.2 GHz processor and 8 GB RAM.

A Novel Table-Based Approach for Design of FinFET Circuits

A new lookup-table (LUT) approach, based on normalization of the drain current with an I D-V G template, is proposed for simulation of MOS transistor circuits. The LUT approach is validated by considering two examples and by comparing the LUT results with mixed-mode (device-circuit) simulation results. This approach is implemented in a circuit simulator and integrated, for the first time, with an optimizer to enable efficient design of circuits, particularly those involving novel technologies for which compact models are not fully developed. Three FinFET-based circuits are designed to demonstrate the effectiveness of the proposed environment. Furthermore, it is shown that the table-based platform can take into account variations in process, supply voltage, and temperature during the design.

Performance Evaluation and Comparative Analysis of Network Firewalls

Firewalls are no longer just perimeter devices for the data center, but should be weaved into the fabric of the network from edge to edge such as to offer security layered in-depth and ubiquitous. The next evolution of the firewall has to combine dynamic policy-based security with performance, rapid scaling, high availability and application intelligence. Today, increasing attention is paid to network firewall design quality due to regulations such as the Sarbanes-Oxley act, CobiT framework, the Payment-Card Industry Data Security Standard (PCI DSS) and the NIST standard. All these regulations include specific sections dealing with firewall configuration, management and audit. This paper is a humble attempt to examine various types of firewalls operational as on today and cross reference each firewall operation with causes and effects of weaknesses in their operation. In addition, we analyze reported problems with existing firewalls. Detailed analysis and comparison is done in terms of cost, security, operational ease and implementation of Open source packet filter (PF) firewall, Checkpoint SPLAT and Cisco ASA in a testing environment with laboratory generated traffic. Various throughputs and connections statistics were used as benchmark for performance comparison. The results indicated that Cisco ASA outperforms its peers in most performance criterions. Checkpoint SPLAT and OpenBSD PF also provides reasonably good and competitive performance. The results reported in this paper will also be useful in comparing vendors to procure firewall based on ones own organizational business requirements.

Parameter extraction for PSP MOSFET model using hierarchical particle swarm optimization

The particle swarm optimization (PSO) algorithm is applied to the problem of MOSFET parameter extraction for the first time. It is shown to perform significantly better than the genetic algorithm (GA). Several modifications of the basic PSO algorithm have been implemented: (a) Hierarchical PSO (HPSO) in which particles are hierarchically arranged and influenced by the positions of the local and global leaders, (b) memory loss operation due to which a particle forgets its past best position, (c) intensive local search in which the solution space around the global leader is searched with a high resolution, and (d) adaptive inertia which causes the inertia of the particles to change adaptively, depending on the fitness of the population. It is demonstrated that the above features improve the performance of the basic PSO algorithm both for the MOSFET parameter extraction problem and for benchmark functions.

A novel architecture for improving slew rate in FinFET-based op-amps and OTAs

A new architecture for improvement of slew rate (SR) of an op-amp or an operational transconductance amplifier (OTA) in FinFET technology is proposed. The principle of operation of the proposed architecture is based on a set of additional current sources which are switched on, only when OTA should provide a high current, usually for charge or discharge of large load capacitor. Therefore, the power overhead is less compared to conventional high SR designs. The commonly used two-stage Miller-compensated op-amp, designed and optimized in sub 45nm FinFET technology with 1V single supply voltage, is used as an example for demonstration of the proposed method. For the same FinFET technology and with optimal design, it is shown that the slew rate of the op-amp is significantly improved. The slew rate is improved from 273 to 5590V/@ms for an input signal with a rise time of 100ps. The other performance measures such as gain and phase margin remain unchanged with the additional circuitry used for slew rate enhancement.

Parameter extraction for PSP MOSFET model using particle swarm optimization

This paper demonstrates the application of particle swarm optimization (PSO) for parameter extraction of MOSFET model for the first time. Parameters are extracted for PSP MOS model for 65 nm technology NMOS devices. It has been shown that the performance of the PSO algorithm is better than the genetic algorithm (GA) in terms of accuracy and consistency.

A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance

This paper presents a novel table-based approach for efficient statistical analysis of Finfield effect transistor circuits. The proposed approach uses a new scheme for interpolation of look-up tables (LUTs) with respect to process parameters. The effect of various process parameters, viz., channel length, fin width, and effective oxide thickness is studied for three circuits: buffer chain, static random access memory cell, and high-gain low-voltage op-amp. Compared to mixed-mode (device-circuit) simulation, the proposed LUT-based approach is shown to be much faster, thus making it practically a feasible and attractive option for variability analysis especially for emerging technologies where compact models are not available for circuit simulation.

Automated design and optimization of circuits in emerging technologies

A novel table-based environment for automatic design and optimization of FinFET circuits is demonstrated. A new accurate look-up table (LUT) technique is implemented in a circuit simulator and integrated with particle swarm optimization algorithm for efficient circuit designs in novel devices. Op-amp circuits are designed and optimized to demonstrate the accuracy and usefulness of the proposed platform. Further, it is shown that the proposed design methodology can take into account variations in process, supply voltage, and temperature.

Automatic Design of Low-Power Low-Voltage Analog Circuits Using Particle Swarm Optimization with Re-Initialization

In this paper, we present application and effectiveness of Particle Swarm Optimization (PSO) for automatic sizing of analog circuits. An efficient re-initialization strategy is introduced to improve the performance of PSO Algorithm (referred as PSO-R). Four benchmark circuits, namely, (i) CMOS buffer chain, (ii) two-stage CMOS operational amplifier (op-amp), (iii) high-gain low-power low-voltage three-stage CMOS op-amp, and (iv) a recently reported ultra-low-power ultra-low-voltage CMOS Miller operational transconductance amplifier (OTA), are automatically designed using the PSO-R algorithm. For the purpose of comparison, these circuits are also designed using PSO, Hierarchical PSO (HPSO), and Genetic Algorithm (GA). Various CMOS technologies ranging from 0.35 μm down to 0.13 μm are used. PVT (process, voltage, and temperature) variations are taken into account and Spectre tool is used for circuit simulations. The PSO-R algorithm converges to a better solution compared to other algorithms for multiple design trials of various low-power low-voltage op-amp designs. For CMOS ultra-low-power ultra-low-voltage Miller OTA, even performance of the circuit designed by the PSO-R algorithm is better than that of recently reported manual design of the same circuit. For future ultra-low-voltage applications, this OTA is also designed in 0.4 V supply voltage. This 0.4 V OTA gives a DC gain of 75 dB, unity gain frequency of 50 MHZ, and dissipates a power of 550 nW. For this design, PSO-R algorithm has taken 19 minutes of CPU time on average on a Sun system with 1.2 GHz dual core processor and 8 GB RAM.

Parameter extraction for mos model 11 using Particle Swarm Optimization

Efficient DC parameter extraction technique for MOS model 11, level 1100 (MM11) is outlined. The parameters are extracted step-by-step depending upon the characteristics where they play a major role. We have used particle swarm optimization (PSO) and genetic algorithm (GA) to extract parameters for NMOS device with 65 nm technology. To the best of the authors knowledge, this is the first application of PSO algorithm for MOSFET parameter extraction. It has been observed that PSO algorithm performs much better as compared to GA in terms of accuracy and consistency. The proposed extraction strategy has been verified for the same technology for 150 nm and 90 nm devices.