Rajesh H. Zele

CMOS continuous-time current-mode filters for high-frequency applications

Design considerations for high-frequency CMOS continuous-time current-mode filters are presented. The basic building block is a differential current integrator with its gain constant set by a small-signal transconductance and a gate capacitance. A prototype fifth-order low-pass ladder filter implemented in a standard digital 2 mu m n-well CMOS process achieved a -3 dB cutoff frequency (f/sub 0/) of 42 MHz; f/sub 0/ was tunable from 24 to 42 MHZ by varying a reference bias current from 50 to 150 mu A. Using a single 5 V power supply with a nominal reference current of 100 mu A, the five-pole filter dissipated 25.5 mW. The active filter area was 0.056 mm/sup 2//pole. With the minimum input signal defined as the input-referred noise integrated over a 40 MHz bandwidth, and the maximum input signal defined at the 1% total intermodulation distortion (TIMD) level, the measured dynamic range was 69 dB. A third-order elliptic low-pass ladder filter was also integrated in the 2 mu m n-well CMOS process to verify the implementation of finite transmission zeros. >

Low-power CMOS continuous-time filters

A design technique for low-power continuous-time filters using digital CMOS technology is presented. The basic building block is a fully-balanced integrator with its unity-gain frequency determined by a small-signal transconductance and MOSFET gate capacitance. Integrator excess phase shift is reduced using balanced signal paths, and open-loop gain is increased using low-voltage cascode amplifiers. Two-pole bandpass and five-pole lowpass ladder filters have been implemented in a 1.2 /spl mu/m n-well CMOS process. The lowpass prototypes provided 300 kHz-1000 kHz bias-current-tunable -3 dB bandwidth, 67 dB dynamic range with 1% total harmonic distortion (THD), and 30 /spl mu/W/pole (300 kHz bandwidth) power dissipation with a 1.5 V supply; the bandpass prototypes had a tunable center frequency of 300 kHz-1000 kHz, Q of 8.5, and power dissipation of 75 /spl mu/W/pole (525 kHz center frequency) from a 1.5 V supply. The active filter area was 0.1 mm/sup 2//pole for both designs.

A continuous-time current-mode integrator

The authors propose a continuous-time current-mode integrator that offers potential advantages for both higher frequency and lower power monolithic filtering applications. Owing to the small voltage swings inherent in current-mode circuits, the integrator time constant is determined by a small-signal transconductance and an additional MOSFET gate capacitance, while good linearity is maintained using a standard 2- mu m digital CMOS technology. Simulation results predict passband cutoff frequencies exceeding 30 MHz for a five-pole low-pass filter dissipating as little as 2 mW/pole with a 5-V power supply. >

Low-voltage fully-differential CMOS switched-current filters

A 3.3-V fully differential switched-current filtering technique based on current-copier principles is presented. A five-pole lowpass filter has been integrated using the MOSIS standard 1.2-/spl mu/m CMOS n-well technology. Experimental results show that the filter response is accurate for sampling frequencies up to 5 MHz. Measured dynamic range is about 65 dB, and power dissipation is 10 mW per pole. An important feature of this approach is that a designer can optimize circuit performance by optimizing the well-known folded-cascode operational amplifier designs.

Analog logic techniques steer around the noise

CMOS folded source-coupled logic (FSCL) and current-steering logic (CSL), developed to complement conventional CMOS static logic in high-precision mixed-signal applications, are examined. The key feature of FSCL and CSL is the reduction in power-supply noise-current spikes by two orders of magnitude or more compared to conventional CMOS logic. Hence, FSCL and CSL are attractive for the high-speed logic sections of CMOS mixed-mode integrated circuits, while conventional logic is appropriate for the low-speed digital subsections.<<ETX>>

A high gain current-mode operational amplifier

Inaccurate open-loop current gain is a limitation of current-mode circuits. The authors proposed a current-mode operational amplifier (I-opamp) with high open-loop gain that provides accurate closed-loop current-gain characteristics. Negative feedback around the high-gain I-opamp produces an accurate closed-loop current gain insensitive to process, supply, and temperature variations. An analysis of the I-opamp is presented along with possible applications. A topology for a high-gain current-mode differential operational amplifier has been developed and implemented in a 2- mu m n-well CMOS process.<<ETX>>

A 3V-125 MHz CMOS continuous-time filter

A low-voltage high-frequency CMOS fully-differential filtering technique is presented. The low internal voltage characteristic of current-mode circuits allows the operation at power supply voltages as low as 3 V with high dynamic range. The integrator time constant is determined by a MOSFET small-signal transconductance and an additional noncritical MOSFET gate capacitance. For ladder filters derived from doubly-terminated LC prototypes, HSPICE (simulation program with IC emphasis) simulations predict a 3-dB bandwidth of 125 MHz for a three-pole lowpass filter. Power dissipation is 6 mW/pole with a 3-V power supply.<<ETX>>

Fully-differential CMOS current-mode circuits

A CMOS fully-differential current-mode analog signal processing technique has been developed. The basic building block, a 5-V fully differential current-mode operational amplifier (I-OPAMP), has been integrated using the MOSIS 2 mu m n-well CMOS technology. Measured total harmonic distortion (THD) is -70 dB with a peak signal to bias current ratio of 0.5. By simply adding MOS switches, the I-OPAMP topology is easily extended to implement fully differential switched-current (SI) circuits with first-order cancellation of clock-feedthrough effects. A five-pole Chebyshev lowpass fully differential SI ladder filter has also been integrated in the 2- mu m p-well CMOS technology. Measured results show that, with a sampling frequency of 128 kHz, the desired ripple bandwidth of 5 kHz is accurately realized using the fully differential SI structure. Dynamic range is greater than 80 dB with a power dissipation of 14 mW.<<ETX>>

Current-Mode Continuous-Time Filters

A low-voltage high-frequency CMOS fully-balanced filtering technique is presented. The low internal voltage characteristic of current-mode circuits allows the operation at power supply voltages as low as 3-V with high dynamic range. The integrator time-constant is determined by a MOSFET small-signal transconductance and an additional non-critical MOSFET gate capacitance. For ladder filters derived from doubly-terminated LC prototypes, HSPICE simulations predict a -3-dB bandwidth of 125 MHz for a three-pole lowpass filter. Power dissipation is 6 mW/pole with a 3-V power supply.

Fully-differential CMOS current-mode circuits and applications

A CMOS fully differential current-mode analog signal processing technique has been developed. The basic building block, a 5-V fully differential current-mode operational amplifier (I-OPAMP), has been integrated using the MOSIS 2 mu m n-well CMOS technology. Measured total harmonic distortion (THD) is -70 B with a peak signal (1) to a bias current (I) ratio of 0.5. By simply adding MOS switches, the I- OPAMP topology is easily extended to implement fully differential switched-current (SI) circuits with first-order cancellation of clock-feedthrough effects. A five-pole Chebyshev lowpass fully differential SI ladder filter has also been integrated in the 2 mu m p-well CMOS technology. Measured results show that with a sampling frequency of 128 kHz, the desired ripple bandwidth of 5 kHz is accurately realized using the fully differential SI structure.<<ETX>>