Rajesh Sundaram

A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/s DDR Interface

A 3.3V 8Gb NAND flash memory with a synchronous double-data-rate (DDR) interface is designed and fabricated using 3M 50nm technology to meet the requirements of the markets. This paper achieves a NAND flash program throughput of 100 MB/s with quad-plane operation, which is 5x previously reported. I/O read/write throughput of 200MB/s is achieved using a newly developed DDR interface and data path. The chip features a dual interface, supporting both the newly developed synchronous DDR interface as well as the standard, asynchronous NAND flash interface.

A 1.8 V 128 Mb 125 MHz multi-level cell flash memory with flexible read while write

A 128 Mb flash memory with a two bit-per-cell design on a 0.13 /spl mu/m technology achieves a random access time of 55 ns and 125 MHz synchronous operation. The design incorporates a flexible multi-partition memory architecture which allows a program or erase operation to occur in one partition of the memory while bursting data out of another partition. The die is 27.3 mm/sup 2/ with a 0.154 /spl mu/m/sup 2/ cell size.

A 128 Mb NOR flash memory with 3 MB/s program time and low-power write performance by using in-package inductor charge-pump

Improved performance of flash memories requires programming more cells in parallel. This design uses an inductive pump to transfer the energy to a capacitor to achieve the needed voltage. The discrete inductor is bonded atop the die which also includes the control circuitry. With an inductive pump, the current saving in the program mode is 47.5 mA compared to a capacitive pump.